<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/arch/arm/mach-tegra/fuse.c, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
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<updated>2014-07-17T12:36:01+00:00</updated>
<entry>
<title>soc/tegra: Add efuse driver for Tegra</title>
<updated>2014-07-17T12:36:01+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=783c8f4c84451bc444e314a71b447239c6ef6fd9'/>
<id>urn:sha1:783c8f4c84451bc444e314a71b447239c6ef6fd9</id>
<content type='text'>
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.

While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Use a function to get the chip ID</title>
<updated>2014-07-17T11:36:41+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T07:52:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=304664eab93f9e95a8d28fbd9702ede88bb10cc5'/>
<id>urn:sha1:304664eab93f9e95a8d28fbd9702ede88bb10cc5</id>
<content type='text'>
Instead of using a simple variable access to get at the Tegra chip ID,
use a function so that we can run additional code. This can be used to
determine where the chip ID is being accessed without being available.
That in turn will be handy for resolving boot sequence dependencies in
order to convert more code to regular initcalls rather than a sequence
fixed by Tegra SoC setup code.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Sort includes alphabetically</title>
<updated>2014-07-17T11:29:57+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T07:44:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a0524acc94c91c72c2968a76eddc6f3afe82f9f2'/>
<id>urn:sha1:a0524acc94c91c72c2968a76eddc6f3afe82f9f2</id>
<content type='text'>
If these aren't sorted alphabetically, then the logical choice is to
append new ones, however that creates a lot of potential for conflicts
because every change will then add new includes in the same location.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Move includes to include/soc/tegra</title>
<updated>2014-07-17T11:26:47+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-17T11:17:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=306a7f9139318a28063282a15b9f9ebacf09c9b9'/>
<id>urn:sha1:306a7f9139318a28063282a15b9f9ebacf09c9b9</id>
<content type='text'>
In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc</title>
<updated>2013-12-26T19:02:25+00:00</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2013-12-26T19:02:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d578759ed8a6babd9c9aecd4211b3aa5a8e4a27b'/>
<id>urn:sha1:d578759ed8a6babd9c9aecd4211b3aa5a8e4a27b</id>
<content type='text'>
From Stephen Warren:
ARM: tegra: SoC-specific core code changes

This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.

* tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
  ARM: tegra: use section-sized static mappings for LPAE too
  ARM: tegra: don't hard-code DEBUG_LL baud rate
  ARM: tegra: fix DEBUG_LL combined with LPAE
  ARM: tegra: switch FUSE clock on before usage

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: add missing break to fuse initialization code</title>
<updated>2013-12-12T01:09:11+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-12-06T21:31:02+00:00</published>
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<id>urn:sha1:b988ba1b4eba12008107b16fe3714293afdca47e</id>
<content type='text'>
Add a missing break to the switch in tegra_init_fuse() which determines
which SoC the code is running on. This prevents the Tegra30+ fuse
handling code from running on Tegra20.

Fixes: 3bd1ae57f7bb ("ARM: tegra: add fuses as device randomness")
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: switch FUSE clock on before usage</title>
<updated>2013-12-04T19:24:22+00:00</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2013-11-21T02:40:13+00:00</published>
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<id>urn:sha1:cdcb5a074cd3e33e7bdb318487fde8a9e55d6159</id>
<content type='text'>
FUSE clock is enabled by most bootloaders, but we cannot expect it to be
on in all contexts (e.g. kexec).

Ensure the FUSE clock is enabled before any of its registers is touched.
Since FUSE is touched very early during system boot (before the clock
devices are registered), directly manipulate the clock register bit in
case the clock device cannot be acquired.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6</title>
<updated>2013-11-24T00:18:25+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-11-24T00:18:25+00:00</published>
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<id>urn:sha1:26b265cd29dde56bf0901c421eabc7ae815f38c4</id>
<content type='text'>
Pull crypto update from Herbert Xu:
 - Made x86 ablk_helper generic for ARM
 - Phase out chainiv in favour of eseqiv (affects IPsec)
 - Fixed aes-cbc IV corruption on s390
 - Added constant-time crypto_memneq which replaces memcmp
 - Fixed aes-ctr in omap-aes
 - Added OMAP3 ROM RNG support
 - Add PRNG support for MSM SoC's
 - Add and use Job Ring API in caam
 - Misc fixes

[ NOTE! This pull request was sent within the merge window, but Herbert
  has some questionable email sending setup that makes him public enemy
  #1 as far as gmail is concerned.  So most of his emails seem to be
  trapped by gmail as spam, resulting in me not seeing them.  - Linus ]

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (49 commits)
  crypto: s390 - Fix aes-cbc IV corruption
  crypto: omap-aes - Fix CTR mode counter length
  crypto: omap-sham - Add missing modalias
  padata: make the sequence counter an atomic_t
  crypto: caam - Modify the interface layers to use JR API's
  crypto: caam - Add API's to allocate/free Job Rings
  crypto: caam - Add Platform driver for Job Ring
  hwrng: msm - Add PRNG support for MSM SoC's
  ARM: DT: msm: Add Qualcomm's PRNG driver binding document
  crypto: skcipher - Use eseqiv even on UP machines
  crypto: talitos - Simplify key parsing
  crypto: picoxcell - Simplify and harden key parsing
  crypto: ixp4xx - Simplify and harden key parsing
  crypto: authencesn - Simplify key parsing
  crypto: authenc - Export key parsing helper function
  crypto: mv_cesa: remove deprecated IRQF_DISABLED
  hwrng: OMAP3 ROM Random Number Generator support
  crypto: sha256_ssse3 - also test for BMI2
  crypto: mv_cesa - Remove redundant of_match_ptr
  crypto: sahara - Remove redundant of_match_ptr
  ...
</content>
</entry>
<entry>
<title>ARM: tegra: add fuses as device randomness</title>
<updated>2013-10-18T22:28:06+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-09-12T22:51:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=3bd1ae57f7bb3bf79487f7cb88f3ee34c7d58a52'/>
<id>urn:sha1:3bd1ae57f7bb3bf79487f7cb88f3ee34c7d58a52</id>
<content type='text'>
Various fuses on Tegra include information that's unique to an individual
chip, or a subset of chips. Call add_device_randomness() with this data
to perturb the initial state of the random pool.

Suggested-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: remove tegra_chip_uid()</title>
<updated>2013-09-23T20:02:23+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-09-16T15:34:19+00:00</published>
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<id>urn:sha1:ec795ad84c0a8c69723972eae31e60b0d94ab29a</id>
<content type='text'>
Following commit f5b38c5 "crypto: tegra - use kernel entropy instead
of ad-hoc", this function is no longer used. It's also only accurate
for Tegra20 and not later SoCs. So, remove it.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
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