<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/arch/arm/mach-versatile/pci.c, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
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<updated>2015-12-15T22:53:21+00:00</updated>
<entry>
<title>ARM: versatile: switch to DT only booting and remove legacy code</title>
<updated>2015-12-15T22:53:21+00:00</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2015-12-08T20:44:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=16956fed35fecde2201e23458cda193526b19559'/>
<id>urn:sha1:16956fed35fecde2201e23458cda193526b19559</id>
<content type='text'>
With DT support for clocks, irqchips, timers, and PCI now in place, DT
based booting has feature parity with non-DT legacy boot. The final
piece is actually enabling common clock support on Versatile. Enabling
full DT support requires either removing the old Versatile clock code,
updating the legacy boot to use the common clock code, or making DT and
legacy boot mutually exclusive. Given that removing legacy boot code is
the goal anyway, I am going with the 1st option.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Russell King &lt;linux@arm.linux.org.uk&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>ARM: PCI: versatile: Fix SMAP register offsets</title>
<updated>2013-09-04T21:53:33+00:00</updated>
<author>
<name>Peter Maydell</name>
<email>peter.maydell@linaro.org</email>
</author>
<published>2013-08-22T16:47:50+00:00</published>
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<id>urn:sha1:99f2b130370b904ca5300079243fdbcafa2c708b</id>
<content type='text'>
The SMAP register offsets in the versatile PCI controller code were
all off by four.  (This didn't have any observable bad effects
because on this board PHYS_OFFSET is zero, and (a) writing zero to
the flags register at offset 0x10 has no effect and (b) the reset
value of the SMAP register is zero anyway, so failing to write SMAP2
didn't matter.)

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: PCI: versatile: Fix PCI I/O</title>
<updated>2013-09-04T21:53:26+00:00</updated>
<author>
<name>Peter Maydell</name>
<email>peter.maydell@linaro.org</email>
</author>
<published>2013-08-22T16:47:49+00:00</published>
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<id>urn:sha1:829f9fedee30cde2ec15e88d57ec11074db791e2</id>
<content type='text'>
The versatile PCI controller code was confused between the
PCI I/O window (at 0x43000000) and the first PCI memory
window (at 0x44000000). Pass the correct base address to
pci_remap_io() so that PCI I/O accesses work.

Since the first PCI memory window isn't used at all (it's
an odd size), rename the associated variables and labels
so that it's clear that it isn't related to the I/O window.

This has been tested and confirmed to fix PCI I/O accesses
both on physical PB926+PCI backplane hardware and on QEMU.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: PCI: versatile: Fix map_irq function to match hardware</title>
<updated>2013-09-04T21:52:52+00:00</updated>
<author>
<name>Peter Maydell</name>
<email>peter.maydell@linaro.org</email>
</author>
<published>2013-08-22T16:47:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f9b71fef12f0d6ac5c7051cfd87f7700f78c56b6'/>
<id>urn:sha1:f9b71fef12f0d6ac5c7051cfd87f7700f78c56b6</id>
<content type='text'>
The PCI controller code for the Versatile board has never had the
correct IRQ mapping for hardware.  For many years it had an odd
mapping ("all interrupts are int 27") which aligned with the
equivalent bug in QEMU.  However as of commit 1bc39ac5dab265
the mapping changed and no longer matched either hardware or QEMU,
with the result that any PCI card beyond the first in QEMU would
not have functioning interrupts; for example a boot with a SCSI
controller would time out as follows:

 ------------
 sym0: &lt;895a&gt; rev 0x0 at pci 0000:00:0d.0 irq 92
 sym0: SCSI BUS has been reset.
 scsi0 : sym-2.2.3
 [...]
 scsi 0:0:0:0: ABORT operation started
 scsi 0:0:0:0: ABORT operation timed-out.
 scsi 0:0:0:0: DEVICE RESET operation started
 scsi 0:0:0:0: DEVICE RESET operation timed-out.
 scsi 0:0:0:0: BUS RESET operation started
 scsi 0:0:0:0: BUS RESET operation timed-out.
 scsi 0:0:0:0: HOST RESET operation started
 sym0: SCSI BUS has been reset
 ------------

Fix the mapping so that it matches real hardware (checked against the
schematics for PB926 and backplane, and tested against the hardware).
This allows PCI cards using interrupts to work on hardware for the
first time; this change will also work with QEMU 1.5 or later, where
the equivalent bugs in the modelling of the hardware have been fixed.

Although QEMU will attempt to autodetect whether the kernel is
expecting the long-standing "everything is int 27" mapping or the one
hardware has, for certainty we force it into "definitely behave like
hardware mode"; this will avoid unexpected surprises later if we
implement sparse irqs. This is harmless on hardware.

Thanks to Paul Gortmaker for bisecting the problem and finding an initial
solution, to Russell King for providing the correct interrupt mapping,
and to Guenter Roeck for providing an initial version of this patch
and prodding me into relocating the hardware and retesting everything.

Signed-off-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: 7635/1: versatile: fix the PCI IRQ regression</title>
<updated>2013-02-06T09:33:09+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2013-01-28T20:58:22+00:00</published>
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<id>urn:sha1:e3e92a7be6936dff1de80e66b0b683d54e9e02d8</id>
<content type='text'>
The PCI IRQs were regressing due to two things:

- The PCI glue layer was using an hard-coded IRQ 27 offset.
  This caused the immediate regression.

- The SIC IRQ mask was inverted (i.e. a bit was indeed set to
  one for each valid IRQ on the SIC, but accidentally inverted
  in the init call). This has been around forever, but we have
  been saved by some other forgiving code that would reserve
  IRQ descriptors in this range, as the versatile is
  non-sparse.

When the IRQs were bumped up 32 steps so as to avoid using IRQ
zero and avoid touching the 16 legacy IRQs, things broke.

Introduce an explicit valid mask for the IRQs that are active
on the PIC/SIC, and pass that. Use the BIT() macro from
&lt;linux/bitops.h&gt; to make sure we hit the right bits, readily
defined in &lt;mach/platform.h&gt;.

Reported-by: Tetsuo Handa &lt;penguin-kernel@i-love.sakura.ne.jp&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: versatile: use fixed PCI i/o mapping</title>
<updated>2012-07-26T14:09:56+00:00</updated>
<author>
<name>Rob Herring</name>
<email>rob.herring@calxeda.com</email>
</author>
<published>2012-07-09T03:13:54+00:00</published>
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<id>urn:sha1:fe5051754263e7198aa8f415b2e1298c126adb4e</id>
<content type='text'>
Move versatile PCI to fixed i/o mapping and remove io.h.

Signed-off-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Cc: Russell King &lt;linux@arm.linux.org.uk&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>ARM: fix mach-versatile/pci.c warning</title>
<updated>2012-07-04T16:04:57+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2012-07-04T16:04:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=32e1eb59f7042c03cb8dbb598e7c97fddbb62ac2'/>
<id>urn:sha1:32e1eb59f7042c03cb8dbb598e7c97fddbb62ac2</id>
<content type='text'>
arch/arm/mach-versatile/pci.c: In function 'versatile_map_irq':
arch/arm/mach-versatile/pci.c:342: warning: unused variable 'devslot'

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>arm: versatile: fix and enable PCI I/O space</title>
<updated>2012-06-17T01:41:35+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2012-06-11T14:03:58+00:00</published>
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<id>urn:sha1:9b0f7e399238c61f28539daeb65d72a8d7f91966</id>
<content type='text'>
With commit 4d5fc58dbe34b (ARM: remove bunch of now unused
mach/io.h files), the I/O space setup was completely broken on
versatile. This patch fixes that and prepares for further
I/O space clean-up.

I/O space handling on the versatile platform is currently
broken in multiple ways. Most importantly, the ports do
not get mapped into the virtual address space at all.

Also, there is some amount of confusion between PCI I/O
space and other statically mapped MMIO registers in the
platform code:

* The __io_address() macro that is used to access the
  platform register maps to the same __io macro that gets
  used for I/O space.

* The IO_SPACE_LIMIT is set to a value that is much larger
  than the total available space.

* The I/O resource of the PCI bus is set to the physical
  address of the mapping, which is way outside of the
  actual I/O space limit as well as the address range that
  gets decoded by traditional PCI cards.

* No attempt is made to stay outside of the ISA port range
  that some device drivers try access.

* No resource gets requested as a child of ioport_resource,
  but an IORESOURCE_IO type mapping gets requested
  as a child of iomem_resource.

This patch attempts to correct all of the above. This makes
it possible to use virtio-pci based virtual devices as well
as actual PCI cards including those with legacy ISA port
ranges like VGA.

Some of the issues seem to be duplicated on other platforms.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
[rob: update to 3.5-rc2 and io.h cleanup related changes]
Signed-off-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Tested-by: Robert Schwebel &lt;r.schwebel@pengutronix.de&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: PCI: provide a default bus scan implementation</title>
<updated>2012-05-13T16:12:17+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2012-03-10T12:49:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=c23bfc3835173f5229b2503e3b616001a28affad'/>
<id>urn:sha1:c23bfc3835173f5229b2503e3b616001a28affad</id>
<content type='text'>
Most PCI implementations perform simple root bus scanning.  Rather than
having each group of platforms provide a duplicated bus scan function,
provide the PCI configuration ops structure via the hw_pci structure,
and call the root bus scanning function from core ARM PCI code.

Acked-by: Krzysztof Hałasa &lt;khc@pm.waw.pl&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: PCI: get rid of pci_std_swizzle()</title>
<updated>2012-05-13T16:12:16+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2012-03-10T11:39:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=daeb4c0c3bf2df72d0cd6e4330bad9e2e520552b'/>
<id>urn:sha1:daeb4c0c3bf2df72d0cd6e4330bad9e2e520552b</id>
<content type='text'>
Most PCI implementations use the standard PCI swizzle function, which
handles the well defined behaviour of PCI-to-PCI bridges which can be
found on cards (eg, four port ethernet cards.)

Rather than having almost every platform specify the standard swizzle
function, make this the default when no swizzle function is supplied.
Therefore, a swizzle function only needs to be provided when there is
something exceptional which needs to be handled.

This gets rid of the swizzle initializer from 47 files, and leaves us
with just two platforms specifying a swizzle function: ARM Integrator
and Chalice CATS.

Acked-by: Krzysztof Hałasa &lt;khc@pm.waw.pl&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
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