kernel/git/stable/linux.git/arch/arm/mm/cache-v3.S, branch master

ARM: cache: remove ARMv3 support code

2013-03-26T09:55:23+00:00

This is only used by 740t, which is a v4 core and (by my reading of the datasheet for the CPU) ignores CRm for the cp15 cache flush operation, making the v4 cache implementation in cache-v4.S sufficient for this CPU. Tested with 740T core-tile on Integrator/AP baseboard. Acked-by: Hyok S. Choi Acked-by: Greg Ungerer Signed-off-by: Will Deacon

ARM: mm: implement LoUIS API for cache maintenance ops

2012-09-25T10:20:25+00:00

ARM v7 architecture introduced the concept of cache levels and related control registers. New processors like A7 and A15 embed an L2 unified cache controller that becomes part of the cache level hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable do not require a flush of the entire cache hierarchy to DRAM but just the cache levels belonging to the Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems correspond to L1. The current cache flushing API used in cpu_suspend and __cpu_disable, flush_cache_all(), ends up flushing the whole cache hierarchy since for v7 it cleans and invalidates all cache levels up to Level of Coherency (LoC) which cripples system performance when used in hot paths like hotplug and cpuidle. Therefore a new kernel cache maintenance API must be added to cope with latest ARM system requirements. This patch adds flush_cache_louis() to the ARM kernel cache maintenance API. This function cleans and invalidates all data cache levels up to the Level of Unification Inner Shareable (LoUIS) and invalidates the instruction cache for processors that support it (> v7). This patch also creates an alias of the cache LoUIS function to flush_kern_all for all processor versions prior to v7, so that the current cache flushing behaviour is unchanged for those processors. v7 cache maintenance code implements a cache LoUIS function that cleans and invalidates the D-cache up to LoUIS and invalidates the I-cache, according to the new API. Reviewed-by: Santosh Shilimkar Reviewed-by: Nicolas Pitre Signed-off-by: Lorenzo Pieralisi Tested-by: Shawn Guo

ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails

2012-05-02T10:12:49+00:00

The cacheflush syscall can fail for two reasons: (1) The arguments are invalid (nonsensical address range or no VMA) (2) The region generates a translation fault on a VIPT or PIPT cache This patch allows do_cache_op to return an error code to userspace in the case of the above. The various coherent_user_range implementations are modified to return 0 in the case of VIVT caches or -EFAULT in the case of an abort on v6/v7 cores. Reviewed-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Russell King

ARM: mm: cache-v3: Use the new processor struct macros

2011-07-07T14:31:05+00:00

Signed-off-by: Dave Martin

ARM: 6466/1: implement flush_icache_all for the rest of the CPUs

2010-10-28T12:54:28+00:00

Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns: flush_icache_all(). It also implemented this for v6 and v7 but not for v5 and backwards. Without the function pointer in place, we will be calling wrong cache functions. For example with ep93xx we get following: Unable to handle kernel paging request at virtual address ee070f38 pgd = c0004000 [ee070f38] *pgd=00000000 Internal error: Oops: 80000005 [#1] PREEMPT last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.36+ #1) PC is at 0xee070f38 LR is at __dma_alloc+0x11c/0x2d0 pc : [] lr : [] psr: 60000013 sp : c581bde0 ip : 00000000 fp : c0472000 r10: c0472000 r9 : 000000d0 r8 : 00020000 r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000 r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: c000717f Table: c0004000 DAC: 00000017 Process swapper (pid: 1, stack limit = 0xc581a270) [] (__dma_alloc+0x11c/0x2d0) [] (dma_alloc_writecombine+0x1c/0x24) [] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60) [] (ep93xx_pcm_new+0x5c/0x88) [] (snd_soc_instantiate_cards+0x8a8/0xbc0) [] (soc_probe+0xfc/0x134) [] (platform_drv_probe+0x18/0x1c) [] (driver_probe_device+0xb0/0x16c) [] (bus_for_each_drv+0x48/0x84) [] (device_attach+0x50/0x68) [] (bus_probe_device+0x24/0x44) [] (device_add+0x2fc/0x44c) [] (platform_device_add+0x104/0x15c) [] (simone_init+0x60/0x94) [] (do_one_initcall+0xd0/0x1a4) __dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up calling dmac_flush_range(). Now since the entries in the arm920_cache_fns are shifted by one, we jump into address 0xee070f38 which is actually next instruction after the arm920_cache_fns structure. So implement flush_icache_all() for the rest of the supported CPUs using a generic 'invalidate I cache' instruction. Signed-off-by: Mika Westerberg Signed-off-by: Russell King

ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range

2010-02-15T15:22:23+00:00

These are now unused, and so can be removed. Signed-off-by: Russell King Tested-By: Santosh Shilimkar

ARM: dma-mapping: provide per-cpu type map/unmap functions

2010-02-15T15:22:20+00:00

Signed-off-by: Russell King Tested-By: Santosh Shilimkar

ARM: add size argument to __cpuc_flush_dcache_page

2009-12-14T14:53:22+00:00

... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King

[ARM] Remove unnecessary mach/hardware.h includes in arch/arm/mm

2008-11-28T23:20:39+00:00

Signed-off-by: Russell King

[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach

2008-08-07T08:55:48+00:00

This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King