kernel/git/stable/linux.git/arch/arm64/boot, branch linux-5.19.y

arm64: dts: imx8mp: Add snps,gfladj-refclk-lpm-sel quirk to USB nodes

2022-10-24T07:58:27+00:00

[ Upstream commit 5c3d5ecf48ab06c709c012bf1e8f0c91e1fcd7ad ] With this set the SOF/ITP counter is based on ref_clk when 2.0 ports are suspended. snps,dis-u2-freeclk-exists-quirk can be removed as snps,gfladj-refclk-lpm-sel also clears the free running clock configuration bit. Signed-off-by: Alexander Stein Link: https://lore.kernel.org/r/20220915062855.751881-4-alexander.stein@ew.tq-group.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin

arm64: dts: imx8mq-librem5: Add bq25895 as max17055's power supply

2022-10-24T07:58:22+00:00

[ Upstream commit 6effe295e1a87408033c29dbcea9d5a5c8b937d5 ] This allows the userspace to notice that there's not enough current provided to charge the battery, and also fixes issues with 0% SOC values being considered invalid. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin

arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltage

2022-10-24T07:58:22+00:00

[ Upstream commit eef2c0217e02b6c7ed5b10b82ea944127145e113 ] It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly. Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly. Reported-by: Heiko Thiery Signed-off-by: Frieder Schrempf Reviewed-by: Heiko Thiery Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin

arm64: dts: ti: k3-j7200: fix main pinmux range

2022-10-24T07:57:45+00:00

[ Upstream commit 0d0a0b4413460383331088b2203ba09a6971bc3a ] Range size of 0x2b4 was incorrect since there isn't 173 configurable pins for muxing. Additionally there is a non-addressable region in the mapping which requires splitting into two ranges. main_pmx0 -> 67 pins main_pmx1 -> 3 pins Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra Tested-by: Vaishnav Achath Link: https://lore.kernel.org/r/20220919205723.8342-1-mranostay@ti.com Signed-off-by: Sasha Levin

arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types

2022-10-24T07:57:25+00:00

[ Upstream commit 72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd ] As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Link: https://lore.kernel.org/r/20220802101534.1401342-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin

arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt types

2022-10-24T07:57:25+00:00

[ Upstream commit 13dec051c7f139eef345c55a60941843e72128f1 ] As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC") Link: https://lore.kernel.org/r/20220802101534.1401342-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin

arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt types

2022-10-24T07:57:24+00:00

[ Upstream commit f3b7bc89c97b98aa6f157d5f296695af8940a5ac ] As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: f9a2adcc9e908907 ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes") Link: https://lore.kernel.org/r/20220802101534.1401342-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin

arm64: dts: qcom: sdm845-mtp: correct ADC settle time

2022-10-24T07:56:44+00:00

commit 209a04885ab5f76722a1671d0fbf0a5b4bccacec upstream. The PMIC's VADC property for settle time is qcom,hw-settle-time, not qcom,hw-settle-time-us. The latter is used in PMIC's TM ADC. qcom/sdm845-mtp.dtb: pmic@0: adc@3100:adc-chan@4c: 'qcom,hw-settle-time-us' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: d5e12f3823ae ("arm64: dts: qcom: sdm845: mtp: Add vadc channels and thermal zones") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Vinod Koul Reviewed-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220828084341.112146-13-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman

arm64: dts: rockchip: fix upper usb port on BPI-R2-Pro

2022-10-12T07:51:23+00:00

[ Upstream commit 388f9f0a7ff84b7890a24499a3a1fea0cad21373 ] - extcon is no more needed in 5.19 - so drop it commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") - dr_mode was changed from host to otg in rk356x.dtsi commit bc405bb3eeee ("arm64: dts: rockchip: enable otg/drd operation of usb_host0_xhci in rk356x") change it back on board level as id-pin on r2pro is not connected Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220821121929.244112-1-linux@fw-web.de Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

arm64: dts: qcom: sm8350: fix UFS PHY serdes size

2022-10-05T08:40:49+00:00

[ Upstream commit 40e9541959100e017533e18e44d07eed44f91dc5 ] The size of the UFS PHY serdes register region is 0x1c4 and the corresponding 'reg' property should specifically not include the adjacent regions that are defined in the child node (e.g. tx and rx). Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220916093603.24263-1-johan+linaro@kernel.org Signed-off-by: Sasha Levin