kernel/git/stable/linux.git/arch/blackfin/mach-common/cache.S, branch master

arch: remove blackfin port

2018-03-16T09:55:47+00:00

The Analog Devices Blackfin port was added in 2007 and was rather active for a while, but all work on it has come to a standstill over time, as Analog have changed their product line-up. Aaron Wu confirmed that the architecture port is no longer relevant, and multiple people suggested removing blackfin independently because of some of its oddities like a non-working SMP port, and the amount of duplication between the chip variants, which cause extra work when doing cross-architecture changes. Link: https://docs.blackfin.uclinux.org/ Acked-by: Aaron Wu Acked-by: Bryan Wu Cc: Steven Miao Cc: Mike Frysinger Signed-off-by: Arnd Bergmann

Blackfin: SMP: work around anomaly 05000491

2011-03-18T08:01:04+00:00

In order to safely work around anomaly 05000491, we have to execute IFLUSH from L1 instruction sram. The trouble with multi-core systems is that all L1 sram is visible only to the active core. So we can't just place the functions into L1 and call it directly. We need to setup a jump table and place the entry point in external memory. This will call the right func based on the active core. In the process, convert from the manual relocation of a small bit of code into Core B's L1 to the more general framework we already have in place for loading arbitrary pieces of code into L1. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger

Blackfin: split optimization settings more

2011-03-18T08:01:03+00:00

We need to place icache flush funcs into L1 inst sram to work around a hardware anomaly. But this currently breaks SMP support as the L1 inst sram is per-core and cannot be called directly. So in preparation for making that work, split the two options. Further, split out the SMP depend so that we can allow some for SMP. Signed-off-by: Mike Frysinger

Blackfin: iflush: update anomaly 05000491 workaround

2011-03-04T06:27:01+00:00

Recent feedback from design says we need three NOPs in the hardware loop. Signed-off-by: Mike Frysinger

Blackfin: allow cache funcs to be in L1 for IFLUSH Anomaly 05000491

2010-08-06T16:55:47+00:00

Anomaly 05000491 says that IFLUSH cannot have certain types of memory stalls triggered before it has completed in order to function correctly. One such condition is that it be in L1 instruction. So add a config option to move it there, default it to on, and throw up a warning when it is turned off and this anomaly exists. Since the anomaly should be worked around, we can drop the older method of calling IFLUSH multiple times. Signed-off-by: Mike Frysinger Signed-off-by: Sonic Zhang

Blackfin: mass clean up of copyright/licensing info

2009-10-07T08:36:26+00:00

Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger

Blackfin: simplify the do_flush macro

2009-06-12T10:03:48+00:00

Simplify the do_flush macro now that we don't need to take into account a second instruction being used together. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu

Blackfin: fix data cache flushing when doing icache flushing

2009-06-12T10:03:45+00:00

Make sure we flush all data caches and their write buffers before flushing icache, otherwise random edge cases could crop up where stale data is read into icache from external memory. As fallout, punt the combined icache + dcache flush function since we cannot safely do them back to back -- the SSYNC is needed between the dcache flush and the icache flush. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu

Blackfin arch: Fix bug - KGDB single step into the middle of a 4 bytes instruction on bf561 after soft bp is hit

2009-03-05T10:26:59+00:00

Run IFLUSH twice to avoid loading wrong instruction after invalidating icache and following sequence is met. 1) The one instruction address is cached in the icache. 2) This instruction in SDRAM is changed. 3) IFLASH[P0] is executed only once in lackfin_icache_flush_range(). 4) This instruction is executed again, but not the changed new one. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu

Blackfin arch: rewrite blackfin_invalidate_entire_dcache function

2008-11-18T09:48:22+00:00

rewrite blackfin_invalidate_entire_dcache() in C for easier management, better optimization, and so we take all SSYNC anomalies into account Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu