kernel/git/stable/linux.git/arch/mips/alchemy, branch linux-3.5.y

Merge tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtd

2012-06-01T23:55:42+00:00

Pull mtd update from David Woodhouse: - More robust parsing especially of xattr data in JFFS2 - Updates to mxc_nand and gpmi drivers to support new boards and device tree - Improve consistency of information about ECC strength in NAND devices - Clean up partition handling of plat_nand - Support NAND drivers without dedicated access to OOB area - BCH hardware ECC support for OMAP - Other fixes and cleanups, and a few new device IDs Fixed trivial conflict in drivers/mtd/nand/gpmi-nand/gpmi-nand.c due to added include files next to each other. * tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtd: (75 commits) mtd: mxc_nand: move ecc strengh setup before nand_scan_tail mtd: block2mtd: fix recursive call of mtd_writev mtd: gpmi-nand: define ecc.strength mtd: of_parts: fix breakage in Kconfig mtd: nand: fix scan_read_raw_oob mtd: docg3 fix in-middle of blocks reads mtd: cfi_cmdset_0002: Slight cleanup of fixup messages mtd: add fixup for S29NS512P NOR flash. jffs2: allow to complete xattr integrity check on first GC scan jffs2: allow to discriminate between recoverable and non-recoverable errors mtd: nand: omap: add support for hardware BCH ecc ARM: OMAP3: gpmc: add BCH ecc api and modes mtd: nand: check the return code of 'read_oob/read_oob_raw' mtd: nand: remove 'sndcmd' parameter of 'read_oob/read_oob_raw' mtd: m25p80: Add support for Winbond W25Q80BW jffs2: get rid of jffs2_sync_super jffs2: remove unnecessary GC pass on sync jffs2: remove unnecessary GC pass on umount jffs2: remove lock_super mtd: gpmi: add gpmi support for mx6q ...

MIPS: Fix several implicit uses of export.h/module.h

2012-05-15T15:48:50+00:00

These will show up as a build failure once we clean up a misuse of module.h in the mips termios header. Uses export.h: (EXPORT_SYMBOL) arch/mips/cavium-octeon/setup.c arch/mips/pmc-sierra/yosemite/setup.c arch/mips/rb532/devices.c arch/mips/sni/setup.c Uses module.h: (symbol_get/put) arch/mips/alchemy/devboards/db1200.c Uses module.h: (print_modules) arch/mips/kernel/traps.c Signed-off-by: Paul Gortmaker Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3448/ Signed-off-by: Ralf Baechle

mips: Use the plat_nand default partition parser

2012-05-14T03:47:08+00:00

Use the default partition parser, cmdlinepart, provided by the plat_nand driver. Signed-off-by: H Hartley Sweeten Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse

MIPS: Alchemy: Increase minimum timeout for 32kHz timer.

2012-02-20T17:33:18+00:00

Since a clocksource change post 3.2-rc1, tasks on my DB1500 board hang after random amounts of time (from a few minutes to a few hours), regardless of load. Debugging showed that the compare-match register value is a few seconds lower than the current counter value. The minimum value of 8 was initialy determined by a trial-and-error approach. Currently it is sufficient for all Alchemys (without PCI apparently), independent of CPU clock; only the DB1500 and DB1550 boards experience these timer-related tasks hangs now. This patch increases the minimum timeout by 1 (to 9 counter ticks) which seems sufficient since the systems are still working perfectly fine after over 24 hours. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3214/ Signed-off-by: Ralf Baechle

Merge branch 'next/alchemy' into mips-for-linux-next

2012-01-11T14:42:10+00:00

MIPS: Alchemy: db1200: Improve PB1200 detection.

2011-12-08T10:42:16+00:00

The PB1200 has the CPLD located at an address which on the DB1200 is RAM; reading the Board-ID sometimes results in a PB1200 being detected instead (especially during reboots after long uptimes). On the other hand, the address of the DB1200's CPLD is hosting Flash chips on the PB1200. Test for the DB1200 first and additionally do a quick write-test to the hexleds register to make sure we're writing to the CPLD. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3005/ Signed-off-by: Ralf Baechle

MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code.

2011-12-08T10:42:16+00:00

With a generic plat_irq_dispatch (for Alchemy at least) code for both interrupt controller types can coexist in a single kernel image and be autodetected at runtime. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2935/ Signed-off-by: Ralf Baechle

MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller

2011-12-08T10:42:16+00:00

IC and GPIC are now chain handlers of the traditional MIPS IRQ controller. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2933/ Signed-off-by: Ralf Baechle

MIPS: Alchemy: irq: register pm at irq init time

2011-12-08T10:42:15+00:00

No need for a device_initcall. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2934/ Signed-off-by: Ralf Baechle

MIPS: Alchemy: Touchscreen support on DB1100

2011-12-08T10:42:15+00:00

Wire up the ADS7846 touchscreen controller on the DB1100. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2879/ Signed-off-by: Ralf Baechle