kernel/git/stable/linux.git/arch/mips/ath79, branch linux-3.6.y

MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs

2012-10-21T16:32:42+00:00

commit 97541ccfb9db2bb9cd1dde6344d5834438d14bda upstream. Besides the CPU and DDR PLLs, the CPU and DDR frequencies can be derived from other PLLs in the SRIF block on the AR934x SoCs. The current code does not checks if the SRIF PLLs are used and this can lead to incorrectly calculated CPU/DDR frequencies. Fix it by calculating the frequencies from SRIF PLLs if those are used on a given board. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4324/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman

MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x

2012-10-12T20:50:26+00:00

commit 65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39 upstream. The current dividers in the code are wrong and this leads to broken CPU frequency calculation on boards where the fractional part is used. For example, if the SoC is running from a 40MHz reference clock, refdiv=1, nint=14, outdiv=0 and nfrac=31 the real frequency is 579.375MHz but the current code calculates 569.687MHz instead. Because the system time is indirectly related to the CPU frequency the broken computation causes drift in the system time. The correct divider is 2^6 for the CPU PLL and 2^10 for the DDR PLL. Use the correct values to fix the issue. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4305/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman

MIPS: ath79: Use correct IRQ number for the OHCI controller on AR7240

2012-08-17T08:57:27+00:00

The currently assigned IRQ number to the OHCI controller is incorrect for the AR7240 SoC, and that leads to the following error message from the OHCI driver: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver ath79-ohci ath79-ohci: Atheros built-in OHCI controller ath79-ohci ath79-ohci: new USB bus registered, assigned bus number 1 ath79-ohci ath79-ohci: irq 14, io mem 0x1b000000 hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected usb 1-1: new full-speed USB device number 2 using ath79-ohci ath79-ohci ath79-ohci: Unlink after no-IRQ? Controller is probably using the wrong IRQ. Fix this by using the correct IRQ number. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4168/ Signed-off-by: Ralf Baechle

MIPS: ath79: Fix number of GPIO lines for AR724[12]

2012-08-17T08:57:26+00:00

The AR724[12] SoCs have more GPIO lines than the AR7240. Signed-off-by: Gabor Juhos Cc: Cc: linux-mips@linux-mips.org Patchwork: https://http://patchwork.linux-mips.org/patch/4167/ Signed-off-by: Ralf Baechle

MIPS: ath79: add initial support for the Atheros DB120 board

2012-05-15T15:49:11+00:00

Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3517/ Signed-off-by: Ralf Baechle

MIPS: ath79: add PCI registration code for AR934X

2012-05-15T15:49:11+00:00

Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3516/ Signed-off-by: Ralf Baechle

MIPS: ath79: add PCI_AR724X Kconfig symbol

2012-05-15T15:49:11+00:00

The AR724X specific PCI code can be used for the AR934X SoCs, however it can be selected only if SOC_AR724X is set. Introduce a new Kconfig symbol in order to be able to use the code for AR934X as well. Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3514/ Signed-off-by: Ralf Baechle

MIPS: ath79: add WMAC registration code for AR934X

2012-05-15T15:49:10+00:00

Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3513/ Signed-off-by: Ralf Baechle

MIPS: ath79: register UART device for AR934X SoCs

2012-05-15T15:49:10+00:00

Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3512/ Signed-off-by: Ralf Baechle

MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set}

2012-05-15T15:49:09+00:00

Signed-off-by: Gabor Juhos Acked-by: Luis R. Rodriguez Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3511/ Signed-off-by: Ralf Baechle