<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/arch/mips/au1000/Kconfig, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master'/>
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<updated>2008-10-11T15:18:50+00:00</updated>
<entry>
<title>MIPS: Alchemy: rename directory</title>
<updated>2008-10-11T15:18:50+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2008-09-16T17:12:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e8c7c482347574ecdd45c43e32c332d5fc2ece61'/>
<id>urn:sha1:e8c7c482347574ecdd45c43e32c332d5fc2ece61</id>
<content type='text'>
It's more than the au1000 these days.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] kgdb: Remove existing implementation</title>
<updated>2008-07-30T20:54:42+00:00</updated>
<author>
<name>Jason Wessel</name>
<email>jason.wessel@windriver.com</email>
</author>
<published>2008-07-29T20:58:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=8d60a903d986ffa26c41f0092320a3b9da20bfaf'/>
<id>urn:sha1:8d60a903d986ffa26c41f0092320a3b9da20bfaf</id>
<content type='text'>
This patch explicitly removes the kgdb implementation, for mips which
is intended to be followed by a patch that adds a kgdb implementation
for MIPS that makes use of the kgdb core in the kernel.

Signed-off-by: Jason Wessel &lt;jason.wessel@windriver.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Alchemy: fix PCI resource conflict</title>
<updated>2007-12-14T17:34:29+00:00</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sshtylyov@ru.mvista.com</email>
</author>
<published>2007-12-10T17:28:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=dd99d9661c72fe251b842705f2e7cfaa4918a13c'/>
<id>urn:sha1:dd99d9661c72fe251b842705f2e7cfaa4918a13c</id>
<content type='text'>
... by getting the PCI resources back into the 32-bit range -- there's no
need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI
work again while currently the kernel skips the bus scan.

Signed-off-by: Sergei Shtylyov &lt;sshtylyov@ru.mvista.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Only build r4k clocksource for systems that work ok with it.</title>
<updated>2007-11-26T17:26:14+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-11-24T22:33:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=940f6b48a130e0a33cb8bd397dd0e277166470ad'/>
<id>urn:sha1:940f6b48a130e0a33cb8bd397dd0e277166470ad</id>
<content type='text'>
In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] time: Move R4000 clockevent device code to separate configurable file</title>
<updated>2007-10-18T17:11:47+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-10-18T16:48:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=42f77542f4a1c104bb6fbba2e18e04e84415a96b'/>
<id>urn:sha1:42f77542f4a1c104bb6fbba2e18e04e84415a96b</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Alchemy: Fix build by conversion to irq_cpu.c.</title>
<updated>2007-10-17T17:28:48+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-10-17T09:58:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f3e8d1da389fe2e514e31f6e93c690c8e1243849'/>
<id>urn:sha1:f3e8d1da389fe2e514e31f6e93c690c8e1243849</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Kconfig: Enable 64BIT_PHYS_ADDR only through select.</title>
<updated>2007-08-27T01:16:49+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-08-01T23:36:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d806cb2b601c0d6c55b29e1ef9ca2f96f499ea1c'/>
<id>urn:sha1:d806cb2b601c0d6c55b29e1ef9ca2f96f499ea1c</id>
<content type='text'>
The user should not have to have any clue about this setting.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Separate Alchemy processor based boards config</title>
<updated>2007-05-11T13:28:33+00:00</updated>
<author>
<name>Yoichi Yuasa</name>
<email>yoichi_yuasa@tripeaks.co.jp</email>
</author>
<published>2007-05-11T11:44:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=c3543e253a79e1383300953fb9c6f688e8be312d'/>
<id>urn:sha1:c3543e253a79e1383300953fb9c6f688e8be312d</id>
<content type='text'>
Signed-off-by: Yoichi Yuasa &lt;yoichi_yuasa@tripeaks.co.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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