<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/arch/mips/jz4740/setup.c, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/'/>
<updated>2020-09-18T14:34:32+00:00</updated>
<entry>
<title>MIPS: jz4740: Drop all obsolete files</title>
<updated>2020-09-18T14:34:32+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-09-06T19:29:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=b4a30e9c7480603a02d8ad788975428b9c6dc876'/>
<id>urn:sha1:b4a30e9c7480603a02d8ad788975428b9c6dc876</id>
<content type='text'>
Support for Ingenic SoCs is now provided by the arch/mips/generic/ code,
so all files in the arch/mips/jz4740/ folder can dropped, except for the
Kconfig, and the cpu-feature-overrides.h header file.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: ingenic: Hardcode mem size for qi,lb60 board</title>
<updated>2020-07-31T15:48:57+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-07-30T16:12:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=48f5dd56cf2980ff932c6fd98ff5a2c503cde97b'/>
<id>urn:sha1:48f5dd56cf2980ff932c6fd98ff5a2c503cde97b</id>
<content type='text'>
Old Device Tree for the qi,lb60 (aka. Ben Nanonote) did not have a
'memory' node. The kernel would then read the memory controller
registers to know how much RAM was available.

Since every other supported board has had a 'memory' node from the
beginning, we can just hardcode a RAM size of 32 MiB when running with
an old Device Tree without the 'memory' node.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB</title>
<updated>2020-07-31T15:48:19+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-07-30T16:12:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=199c5f080ed695c4b01236e06743a28952403d17'/>
<id>urn:sha1:199c5f080ed695c4b01236e06743a28952403d17</id>
<content type='text'>
The fw_passed_dtb is now properly initialized even when
CONFIG_BUILTIN_DTB is used, so there's no need to handle it in any
particular way here.

Note that the behaviour is slightly different, as the previous code used
the built-in Device Tree unconditionally, while now the built-in Device
Tree is only used when the bootloader did not provide one.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: X2000: Add X2000 system type.</title>
<updated>2020-07-24T09:13:57+00:00</updated>
<author>
<name>周琰杰 (Zhou Yanjie)</name>
<email>zhouyanjie@wanyeetech.com</email>
</author>
<published>2020-07-22T05:21:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=0d10d17bac3d5d4e97d6f008aa3c329a83d3b283'/>
<id>urn:sha1:0d10d17bac3d5d4e97d6f008aa3c329a83d3b283</id>
<content type='text'>
1.Add "PRID_COMP_INGENIC_13" and "PRID_IMP_XBURST2" for X2000.
2.Add X2000 system type for cat /proc/cpuinfo to give out X2000.

Signed-off-by: 周琰杰 (Zhou Yanjie) &lt;zhouyanjie@wanyeetech.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: ingenic: Add support for the JZ4725B SoC</title>
<updated>2020-07-16T08:47:50+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-06-23T18:24:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=c211ab5f5e6e304aee43bb5ef6919fbe4e41ef64'/>
<id>urn:sha1:c211ab5f5e6e304aee43bb5ef6919fbe4e41ef64</id>
<content type='text'>
Add preliminary support for boards based on the JZ4725B SoC from
Ingenic.

The JZ4725B SoC is supposed to be older than the JZ4740 SoC, but its
internals are much closer to what can be found on the JZ4750 and newer
SoCs.

It is low-power SoC with a MIPS32r1 SoC running at ~360 MHz, and no FPU.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: ingenic: Add missing include</title>
<updated>2020-05-20T06:42:31+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-05-19T21:22:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=c9c2e9c596e90fcf9ee0bf16672f7b938f39b913'/>
<id>urn:sha1:c9c2e9c596e90fcf9ee0bf16672f7b938f39b913</id>
<content type='text'>
Add missing include which adds the prototype to plat_time_init().

Fixes: f932449c11da ("MIPS: ingenic: Drop obsolete code, merge the rest in setup.c")
Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Reported-by: kbuild test robot &lt;lkp@intel.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: ingenic: Replace &lt;linux/clk-provider.h&gt; by &lt;linux/of_clk.h&gt;</title>
<updated>2020-05-07T09:59:55+00:00</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2020-05-06T09:04:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=ce61b490965e6d4068641cf33b8ecf6864c3e105'/>
<id>urn:sha1:ce61b490965e6d4068641cf33b8ecf6864c3e105</id>
<content type='text'>
The JZ4740 setup code is not a clock provider, and just needs to call
of_clk_init().

Hence it can include &lt;linux/of_clk.h&gt; instead of &lt;linux/clk-provider.h&gt;.

Fixes: f932449c11dabb4b ("MIPS: ingenic: Drop obsolete code, merge the rest in setup.c")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: ingenic: Drop obsolete code, merge the rest in setup.c</title>
<updated>2020-04-29T21:00:07+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-04-13T15:26:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f932449c11dabb4b0588e30f35c084b910483ca5'/>
<id>urn:sha1:f932449c11dabb4b0588e30f35c084b910483ca5</id>
<content type='text'>
Drop a bootload of 10-years-old dirty code, that is not used anymore, as
it has been replaced with clean code over the ages.

Merge the very few bits left inside setup.c, so that everything is clean
and tidy now.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: X1830: Add X1830 system type.</title>
<updated>2020-01-09T17:48:42+00:00</updated>
<author>
<name>周琰杰 (Zhou Yanjie)</name>
<email>zhouyanjie@wanyeetech.com</email>
</author>
<published>2019-12-09T05:10:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=b9bb868e2fc169b7917392eb41c84bc7436a8022'/>
<id>urn:sha1:b9bb868e2fc169b7917392eb41c84bc7436a8022</id>
<content type='text'>
1.Add X1830 system type for cat /proc/cpuinfo to give out X1830.
2.Change "PRID_IMP_XBURST" to "PRID_IMP_XBURST_REV1" and add a
  new "PRID_IMP_XBURST_REV2" for new Ingenic CPUs which has
  XBurst with MXU2 SIMD ISA.

Notice:
1."PRID_IMP_XBURST_REV2" is corresponds to the latest XBurst
  processor with 128bit MXU2 SIMD instruction set, not the upcoming
  XBurst2 processor. This version of the processors fixes issues
  such as BTB and HPTLB.
2.In order to simplify and reuse the code, the "c-&gt;cputype" and
  the "c-&gt;writecombine" and the "__cpu_name[cpu]" in the original
  "PRID_IMP_XBURST" (now is "PRID_IMP_XBURST_REV1") are removed,
  and the corresponding settings are abtained through fall-through
  to "PRID_IMP_XBURST_REV2", which will cause the name that was
  previously mistakenly called "JZRISC" to become to the real name
  "XBurst".

Signed-off-by: 周琰杰 (Zhou Yanjie) &lt;zhouyanjie@wanyeetech.com&gt;
Signed-off-by: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: yamada.masahiro@socionext.com
Cc: tglx@linutronix.de
Cc: chenhc@lemote.com
Cc: tbogendoerfer@suse.de
Cc: paul.burton@mips.com
Cc: paul@crapouillou.net
Cc: jhogan@kernel.org
Cc: fancer.lancer@gmail.com
Cc: ralf@linux-mips.org
Cc: jiaxun.yang@flygoat.com
</content>
</entry>
<entry>
<title>MIPS: jz4740: Drop dead code</title>
<updated>2019-07-30T17:41:54+00:00</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2019-07-25T22:02:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=7f428252dbd0adc91317ae7ea27d7e27b70df1f6'/>
<id>urn:sha1:7f428252dbd0adc91317ae7ea27d7e27b70df1f6</id>
<content type='text'>
Remove all the source files that are not used anywhere anymore.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Tested-by: Artur Rojek &lt;contact@artur-rojek.eu&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
</content>
</entry>
</feed>
