<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/arch/x86/hyperv, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/'/>
<updated>2026-08-26T23:47:40+00:00</updated>
<entry>
<title>Merge tag 'hyperv-next-signed-20260826' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux</title>
<updated>2026-08-26T23:47:40+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-08-26T23:47:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=5e6ff28676dd92a608eb00eeb8d1319ad34024dc'/>
<id>urn:sha1:5e6ff28676dd92a608eb00eeb8d1319ad34024dc</id>
<content type='text'>
Pull hyperv updates from Wei Liu:

 - Decrypt netvsc buffer on contiguous direct-map addresses (Kameron
   Carr)

 - Drop WS2012/2012R2 &amp; Win8/8.1 Hyper-V support (Michael Kelley)

 - Use more meaningful errnos for hypercall status code (Hardik Garg)

 - Fix lost interrupts on CPU hot-unplug for Hyper-V PCI/MSI (Naman
   Jain)

 - Reserve more MSHV vectors for Linux root partition (Wei Liu)

* tag 'hyperv-next-signed-20260826' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux:
  clocksource: hyper-v: Remove support for stimer interrupts in message mode
  scsi: storvsc: Remove support for storvsc protocol of old Hyper-V hosts
  hv_netvsc: Remove GPADL teardown special case for old Hyper-V hosts
  hv_sock: Remove check for old Hyper-V hosts
  Drivers: hv: Remove support for WS2012/2012R2 &amp; Win8/8.1 version of Hyper-V
  hv_netvsc: Allocate send/receive buffers using vmbus_alloc_buffer()
  Drivers: hv: vmbus: Add vmbus_alloc_buffer()/vmbus_free_buffer() for CoCo VMs
  Drivers: hv: vmbus: add vmbus_establish_gpadl_caller_decrypted()
  Drivers: hv: vmbus: Skip VMBus module cleanup for non-nested root partition
  x86/hyperv: reserve more vectors
  PCI: hv: Set irq_retrigger callback for the Hyper-V PCI MSI irqchip
  Drivers: hv: Use meaningful errnos for hypercall status codes
</content>
</entry>
<entry>
<title>clocksource: hyper-v: Remove support for stimer interrupts in message mode</title>
<updated>2026-08-24T00:36:14+00:00</updated>
<author>
<name>Michael Kelley</name>
<email>mhkelley58@gmail.com</email>
</author>
<published>2026-08-05T20:37:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=be0cfab740e58b70047ef6e7e3d578f00ed5d258'/>
<id>urn:sha1:be0cfab740e58b70047ef6e7e3d578f00ed5d258</id>
<content type='text'>
In Hyper-V versions prior to WS2016/Win10, Hyper-V synthetic timers
interrupt the guest by delivering a message that is initially handled
by the Linux VMBus driver. Starting with WS2016/Win10, Hyper-V can
deliver stimer interrupts directly to an assigned interrupt vector
without involving the VMBus driver. This is called "Direct Mode".

With the overall removal of Linux support for running on Hyper-V
hosts earlier than WS2016 and Windows 10, it's no longer necessary
to support the legacy message-based delivery. Remove that delivery
mechanism and always use Direct Mode. If for some reason, the
Hyper-V host does not enumerate Direct Mode, output an error
message but continue to run using the LAPIC timer instead of an
stimer.

With these changes, the VMBus driver no longer calls the stimer
interrupt service routine. This removal has a broader benefit in
unblocking the disentangling of VMBus code and stimer code, as
they should be independent of each other. The final disentangling
will come as a follow-on patch set.

Signed-off-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Signed-off-by: Wei Liu &lt;wei.liu@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-08-18T21:02:15+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-08-18T21:02:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=8dcef8882aad8f1b8668d1c39968cde99312aa3c'/>
<id>urn:sha1:8dcef8882aad8f1b8668d1c39968cde99312aa3c</id>
<content type='text'>
Pull x86 MSR updates from Ingo Molnar:

 - Streamline the x86 MSR handling APIs along the 64-bit variants,
   simplifying the interfaces.

   Removal of the old APIs is planned for the next cycle, to reduce
   churn &amp; integration pain (Juergen Gross)

* tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits)
  x86/mce: Work around build warning after MSR-interface switch
  cpufreq: Stop using 32-bit MSR interfaces
  x86/featctl: Stop using 32-bit MSR interfaces
  KVM/x86: Stop using 32-bit MSR interfaces
  x86/mtrr: Stop using 32-bit MSR interfaces
  acpi: Stop using 32-bit MSR interfaces
  powercap: Stop using 32-bit MSR interfaces
  thermal/intel: Stop using 32-bit MSR interfaces
  x86/olpc: Stop using 32-bit MSR interfaces
  x86/hyperv: Stop using 32-bit MSR interfaces
  hwmon: Stop using 32-bit MSR interfaces
  EDAC: Stop using 32-bit MSR interfaces
  x86/cpu: Stop using 32-bit MSR interfaces
  x86/apic: Stop using 32-bit MSR interfaces
  x86/resctrl: Stop using 32-bit MSR interfaces
  x86/tsc: Stop using 32-bit MSR interfaces
  x86/amd: Stop using 32-bit MSR interfaces
  x86/pci: Stop using 32-bit MSR interfaces
  x86/hygon: Stop using 32-bit MSR interfaces
  x86/mce: Stop using 32-bit MSR interfaces
  ...
</content>
</entry>
<entry>
<title>x86/paravirt: Use static_call() for the paravirt spinlock ops</title>
<updated>2026-08-07T15:58:09+00:00</updated>
<author>
<name>Peter Zijlstra</name>
<email>peterz@infradead.org</email>
</author>
<published>2026-08-04T07:15:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=fc6ad5eadcd1694d2f1ee2717c8024efd8152e20'/>
<id>urn:sha1:fc6ad5eadcd1694d2f1ee2717c8024efd8152e20</id>
<content type='text'>
queued_spin_lock_slowpath() and queued_spin_unlock() are dispatched
through pv_ops_lock via the paravirt-ops ALTERNATIVE machinery, which
picks the target (native inline store / hypervisor call) once at boot
and cannot change at runtime.

Convert both to static_call(). The site becomes a direct call patched in
place (one byte smaller), and on native the unlock still collapses to
the inline "movb $0, (%rdi)" store, so the fast path is unchanged.

Unlike the ALTERNATIVE mechanism, a static_call() target can also be
updated at runtime via static_call_update(). This is a prerequisite for
the contended_release tracepoint, which has to swap in a traced unlock
while the system is running.

[ ilvokhin: commit message; fix PARAVIRT_SPINLOCKS=n build; teach
  __static_call_validate() about the inline unlock insn; make the
  slowpath site module-safe: static_call_mod() +
  EXPORT_STATIC_CALL_TRAMP(); pass @lock to the callee-save unlock,
  fixing a boot hang under CALL_DEPTH_TRACKING. Boot tested native + KVM
  PV guest. ]

Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Co-developed-by: Dmitry Ilvokhin &lt;d@ilvokhin.com&gt;
Signed-off-by: Dmitry Ilvokhin &lt;d@ilvokhin.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Link: https://lore.kernel.org/all/20260603120811.GW3493090@noisy.programming.kicks-ass.net/
Link: https://patch.msgid.link/9a32ae399eb804a02a31af04dcabe7e7ee4f3fdf.1785778551.git.d@ilvokhin.com
</content>
</entry>
<entry>
<title>x86/hyperv: Stop using 32-bit MSR interfaces</title>
<updated>2026-07-03T09:33:59+00:00</updated>
<author>
<name>Juergen Gross</name>
<email>jgross@suse.com</email>
</author>
<published>2026-06-29T06:05:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f1b599106414c72695298a70605efc36ea4988cc'/>
<id>urn:sha1:f1b599106414c72695298a70605efc36ea4988cc</id>
<content type='text'>
The 32-bit MSR interface rdmsr() is planned to be removed. Use the
related 64-bit variant instead.

This conversion also simplifies the code a bit.

Signed-off-by: Juergen Gross &lt;jgross@suse.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: K. Y. Srinivasan &lt;kys@microsoft.com&gt;
Cc: Dexuan Cui &lt;decui@microsoft.com&gt;
Cc: Haiyang Zhang &lt;haiyangz@microsoft.com&gt;
Cc: Long Li &lt;longli@microsoft.com&gt;
Cc: Wei Liu &lt;wei.liu@kernel.org&gt;
Link: https://patch.msgid.link/20260629060526.3638272-28-jgross@suse.com
</content>
</entry>
<entry>
<title>Merge tag 'hyperv-next-signed-20260621' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux</title>
<updated>2026-06-22T15:06:13+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-06-22T15:06:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=6e869de3a1b9ef9f096223e0e7f30c727de4f6bc'/>
<id>urn:sha1:6e869de3a1b9ef9f096223e0e7f30c727de4f6bc</id>
<content type='text'>
Pull hyperv updates from Wei Liu:

 - Use wakeup mailbox to boot APs in Hyper-V VTL2 TDX guests (Yunhong
   Jiang, Ricardo Neri)

 - Move the Hyper-V IOMMU to its own subdirectory (Mukesh Rathor)

 - Cosmetic changes to mshv and balloon driver (Junrui Luo, Markus
   Elfring)

* tag 'hyperv-next-signed-20260621' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux:
  mshv: add bounds check on vp_index in mshv_intercept_isr()
  hv_balloon: Simplify data output in hv_balloon_debug_show()
  x86/hyperv: Cosmetic changes in irqdomain.c for readability
  iommu/hyperv: Create hyperv subdirectory under drivers/iommu
  x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs
  x86/hyperv/vtl: Mark the wakeup mailbox page as private
  x86/acpi: Add a helper to get the address of the wakeup mailbox
  x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests
  x86/realmode: Make the location of the trampoline configurable
  x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform()
  x86/dt: Parse the Wakeup Mailbox for Intel processors
  dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors
  x86/acpi: Add functions to setup and access the wakeup mailbox
  x86/topology: Add missing struct declaration and attribute dependency
</content>
</entry>
<entry>
<title>x86/hyperv: Cosmetic changes in irqdomain.c for readability</title>
<updated>2026-06-08T05:59:49+00:00</updated>
<author>
<name>Mukesh R</name>
<email>mrathor@linux.microsoft.com</email>
</author>
<published>2026-06-01T22:51:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=982cb55bec4a8aa73569dba4739a3de1ee2c25d9'/>
<id>urn:sha1:982cb55bec4a8aa73569dba4739a3de1ee2c25d9</id>
<content type='text'>
Make cosmetic changes:
 o Rename struct pci_dev *dev to *pdev since there are cases of
   struct device *dev in the file and all over the kernel
 o Rename hv_build_pci_dev_id to hv_build_devid_type_pci in anticipation
   of building different types of device ids
 o Fix checkpatch.pl issues with return and extraneous printk
 o Replace spaces with tabs
 o Rename struct hv_devid *xxx to struct hv_devid *hv_devid given code
   paths involve many types of device ids
 o Fix indentation in a large if block by using goto.

There are no functional changes.

Reviewed-by: Souradeep Chakrabarti &lt;schakrabarti@linux.microsoft.com&gt;
Reviewed-by: Anirudh Rayabharam (Microsoft) &lt;anirudh@anirudhrb.com&gt;
Signed-off-by: Mukesh R &lt;mrathor@linux.microsoft.com&gt;
Signed-off-by: Wei Liu &lt;wei.liu@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs</title>
<updated>2026-05-28T20:01:26+00:00</updated>
<author>
<name>Ricardo Neri</name>
<email>ricardo.neri-calderon@linux.intel.com</email>
</author>
<published>2026-03-04T23:41:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=7a035678fc2bdee81881170764ef08a91a076147'/>
<id>urn:sha1:7a035678fc2bdee81881170764ef08a91a076147</id>
<content type='text'>
The hypervisor is an untrusted entity for TDX guests. It cannot be used
to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot
be used.

Instead, the virtual firmware boots the secondary CPUs and places them in
a state to transfer control to the kernel using the wakeup mailbox. The
firmware enumerates the mailbox via either an ACPI table or a DeviceTree
node.

If the wakeup mailbox is present, the kernel updates the APIC callback
wakeup_secondary_cpu_64() to use it.

Reviewed-by: Dexuan Cui &lt;decui@microsoft.com&gt;
Reviewed-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Signed-off-by: Ricardo Neri &lt;ricardo.neri-calderon@linux.intel.com&gt;
Signed-off-by: Dexuan Cui &lt;dexuan@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/hyperv/vtl: Mark the wakeup mailbox page as private</title>
<updated>2026-05-28T20:01:26+00:00</updated>
<author>
<name>Yunhong Jiang</name>
<email>yunhong.jiang@linux.intel.com</email>
</author>
<published>2026-03-04T23:41:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=80200341197a799fe39da4e9da61bde4d23ec7ec'/>
<id>urn:sha1:80200341197a799fe39da4e9da61bde4d23ec7ec</id>
<content type='text'>
The current code maps MMIO devices as shared (decrypted) by default in a
confidential computing VM.

In a TDX environment, secondary CPUs are booted using the Multiprocessor
Wakeup Structure defined in the ACPI specification. The virtual firmware
and the operating system function in the guest context, without
intervention from the VMM. Map the physical memory of the mailbox as
private. Use the is_private_mmio() callback.

Signed-off-by: Yunhong Jiang &lt;yunhong.jiang@linux.intel.com&gt;
Signed-off-by: Ricardo Neri &lt;ricardo.neri-calderon@linux.intel.com&gt;
Signed-off-by: Dexuan Cui &lt;dexuan@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests</title>
<updated>2026-05-28T20:01:25+00:00</updated>
<author>
<name>Yunhong Jiang</name>
<email>yunhong.jiang@linux.intel.com</email>
</author>
<published>2026-03-04T23:41:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=aa7719039bd9e378c8c134b8ce5fa5f4e13cda73'/>
<id>urn:sha1:aa7719039bd9e378c8c134b8ce5fa5f4e13cda73</id>
<content type='text'>
The hypervisor is an untrusted entity for TDX guests. It cannot be used
to boot secondary CPUs - neither via hypercalls nor the INIT assert,
de-assert, plus Start-Up IPI messages.

Instead, the platform virtual firmware boots the secondary CPUs and
puts them in a state to transfer control to the kernel. This mechanism uses
the wakeup mailbox described in the Multiprocessor Wakeup Structure of the
ACPI specification. The entry point to the kernel is trampoline_start64.

Allocate and setup the trampoline using the default x86_platform callbacks.

The platform firmware configures the secondary CPUs in long mode. It is no
longer necessary to locate the trampoline under 1MB memory. After handoff
from firmware, the trampoline code switches briefly to 32-bit addressing
mode, which has an addressing limit of 4GB. Set the upper bound of the
trampoline memory accordingly.

Reviewed-by: Dexuan Cui &lt;decui@microsoft.com&gt;
Reviewed-by: Michael Kelley &lt;mhklinux@outlook.com&gt;
Signed-off-by: Yunhong Jiang &lt;yunhong.jiang@linux.intel.com&gt;
Signed-off-by: Ricardo Neri &lt;ricardo.neri-calderon@linux.intel.com&gt;
Signed-off-by: Dexuan Cui &lt;dexuan@kernel.org&gt;
</content>
</entry>
</feed>
