kernel/git/stable/linux.git/drivers/clk/Makefile, branch linux-4.7.y

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2016-05-21T03:18:12+00:00

Pull clk updates from Stephen Boyd: "It's the usual big pile of driver updates and additions, but we do have a couple core changes in here as well. Core: - CLK_IS_CRITICAL support has been added. This should allow drivers to properly express that a certain clk should stay on even if their prepare/enable count drops to 0 (and in turn the parents of these clks should stay enabled). - A clk registration API has been added, clk_hw_register(), and an OF clk provider API has been added, of_clk_add_hw_provider(). These APIs have been put in place to further split clk providers from clk consumers, with the goal being to have clk providers never deal with struct clk pointers at all. Conversion of provider drivers is on going. clkdev has also gained support for registering clk_hw pointers directly so we can convert drivers that don't use devicetree. New Drivers: - Marvell ap806 and cp110 system controllers (with clks inside!) - Hisilicon Hi3519 clock and reset controller - Axis ARTPEC-6 clock controllers - Oxford Semiconductor OXNAS clock controllers - AXS10X I2S PLL - Rockchip RK3399 clock and reset controller Updates: - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos 542x SoCs, and some more clk ID exporting for bus frequency scaling - Proper BCM2835 PCM clk support and various other clks - i.MX clk updates for i.MX6SX, i.MX7, and VF610 - Renesas updates for R-Car H3 - Tegra210 got updates for DisplayPort and HDMI 2.0 - Rockchip driver refactorings and fixes due to adding RK3399 support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits) clk: fix critical clock locking clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM clk: ingenic: Allow divider value to be divided clk: sunxi: Add display and TCON0 clocks driver clk: rockchip: drop old_rate calculation on pll rate changes clk: rockchip: simplify GRF handling in pll clocks clk: rockchip: lookup General Register Files in rockchip_clk_init clk: rockchip: fix the rk3399 sdmmc sample / drv name clk: mvebu: new driver for Armada CP110 system controller dt-bindings: arm: add DT binding for Marvell CP110 system controller clk: mvebu: new driver for Armada AP806 system controller clk: hisilicon: add CRG driver for hi3519 soc clk: hisilicon: export some hisilicon APIs to modules reset: hisilicon: add reset controller driver for hisilicon SOCs clk: bcm/kona: Do not use sizeof on pointer type clk: qcom: msm8916: Fix crypto clock flags clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0 clk/axs10x: Add I2S PLL clock driver clk: imx7d: fix ahb clock mux 1 clk: fix comment of devm_clk_hw_register() ...

CLK: microchip: Add Microchip PIC32 clock driver.

2016-05-13T13:30:25+00:00

This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle

clk/axs10x: Add I2S PLL clock driver

2016-05-06T17:35:04+00:00

The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: Jose Abreu Acked-by: Rob Herring Signed-off-by: Stephen Boyd

clk: Add Oxford Semiconductor OXNAS Standard Clocks

2016-04-21T21:20:07+00:00

Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support. Signed-off-by: Neil Armstrong [sboyd@codeaurora.org: Drop NULL/continue check in registration loop] Signed-off-by: Stephen Boyd

Merge branch 'clk-artpec6' into clk-next

2016-04-15T23:02:46+00:00

* clk-artpec6: clk: add artpec-6 clock controller clk: add device tree binding for Artpec-6 clock controller

clk: add artpec-6 clock controller

2016-04-15T23:02:16+00:00

Add a driver for the main clock controller of the Artpec-6 Soc. Signed-off-by: Lars Persson [sboyd@codeaurora.org: Reformatted driver structure and of match] Signed-off-by: Stephen Boyd

clk: unconditionally recurse into clk/mvebu/

2016-04-02T01:25:54+00:00

The drivers/clk/mvebu directory is only being built when CONFIG_PLAT_ORION=y. As we are going to support additional mvebu platforms in drivers/clk/mvebu, which don't have CONFIG_PLAT_ORION=y, we need to recurse into this directory regardless of the value of CONFIG_PLAT_ORION. Since all files in drivers/clk/mvebu/ are already conditionally compiled depending on various Kconfig options, we can recurse unconditionally into drivers/clk/mvebu without any other change. Signed-off-by: Thomas Petazzoni Signed-off-by: Stephen Boyd

clk: renesas: move drivers to renesas directory

2016-03-03T19:22:53+00:00

This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven Signed-off-by: Stephen Boyd

Merge branch 'clk-ti' into clk-next

2016-03-02T00:23:40+00:00

Conflicts: drivers/clk/Kconfig

clk: ti: Allow COMPILE_TEST to build selected drivers

2016-03-02T00:21:25+00:00

The arch independent drivers can be build testeed with COMPILE_TEST. Let's allow that for drivers/clk/ti. Signed-off-by: Tony Lindgren Signed-off-by: Michael Turquette