clk: cix: add sky1 audss clock controller

2026-07-28T15:25:29+00:00

Add a platform driver for the Cix Sky1 AUDSS CRU. The driver maps the CRU registers and registers mux, divider and gate clocks for DSP, SRAM, HDA, DMAC, I2S, mailbox, watchdog and timer blocks. Four SoC-level audio reference clocks are enabled as inputs to the internal clock tree. The driver releases the AUDSS NOC reset, enables runtime PM and instantiates the auxiliary reset device. Signed-off-by: Joakim Zhang Reviewed-by: Brian Masney Signed-off-by: Brian Masney

kernel/git/stable/linux.git/drivers/clk/cix, branch master

clk: cix: add sky1 audss clock controller