kernel/git/stable/linux.git/drivers/clk/mediatek, branch linux-6.13.y

clk: mediatek: mt2701-mm: add missing dummy clk

2025-02-17T10:36:24+00:00

commit 67aea188f23a5dde51c31a720ccf66aed0ce4187 upstream. Add dummy clk which was missed during the conversion to mtk_clk_pdev_probe() and is required for the existing DT bindings to keep working. Fixes: 65c10c50c9c7 ("clk: mediatek: Migrate to mtk_clk_pdev_probe() for multimedia clocks") Cc: stable@vger.kernel.org Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/9de23440fcba1ffef9e77d58c9f505105e57a250.1734300668.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: mediatek: mt2701-img: add missing dummy clk

2025-02-17T10:36:24+00:00

commit 366640868ccb4a7991aebe8442b01340fab218e2 upstream. Add dummy clk for index 0 which was missed during the conversion to mtk_clk_simple_probe(). Fixes: 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") Cc: stable@vger.kernel.org Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/d677486a5c563fe5c47aa995841adc2aaa183b8a.1734300668.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: mediatek: mt2701-bdp: add missing dummy clk

2025-02-17T10:36:23+00:00

commit fd291adc5e9a4ee6cd91e57f148f3b427f80647b upstream. Add dummy clk for index 0 which was missed during the conversion to mtk_clk_simple_probe(). Fixes: 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") Cc: stable@vger.kernel.org Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/b8526c882a50f2b158df0eccb4a165956fd8fa13.1734300668.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe

2025-02-17T10:36:23+00:00

commit 5fba40be5fbad563914e3ce9d5129a6baaea1ff5 upstream. Some of the audio subsystem clocks defined in clk-mt2701.h aren't actually used by the driver. This broke conversion to mtk_clk_simple_probe which expects that the highest possible clk id is defined by the ARRAY_SIZE. Add additional dummy clocks to fill the gaps and remain compatible with the existing DT bindings. Fixes: 0f69a423c458 ("clk: mediatek: Switch to mtk_clk_simple_probe() where possible") Cc: stable@vger.kernel.org Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/a07584d803af57b9ce4b5df5e122c09bf5a56ac9.1734300668.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe

2025-02-17T10:36:23+00:00

commit 7c8746126a4e256fcf1af9174ee7d92cc3f3bc31 upstream. Commit 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") broke DT bindings as the highest index was reduced by 1 because the id count starts from 1 and not from 0. Fix this, like for other drivers which had the same issue, by adding a dummy clk at index 0. Fixes: 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") Cc: stable@vger.kernel.org Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/b126a5577f3667ef19b1b5feea5e70174084fb03.1734300668.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers

2024-11-14T20:52:14+00:00

Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana Link: https://lore.kernel.org/r/20241106111402.200940-3-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd

clk: mediatek: mt6735-apmixedsys: Fix an error handling path in clk_mt6735_apmixed_probe()

2024-11-14T20:51:47+00:00

If an error occurs after a successful mtk_alloc_clk_data(), mtk_free_clk_data() should be called, as already done in the .remove() function. Switch to mtk_devm_alloc_clk_data() in order to fix the memory leak in the probe function, and simplify the remove function. Fixes: 43c04ed79189 ("clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/89ad840e7a484eaf4727470824acfe0fdc60fcef.1729871146.git.christophe.jaillet@wanadoo.fr Tested-by: Yassine Oudjana Signed-off-by: Stephen Boyd

clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp

2024-10-17T22:24:48+00:00

Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when setting mfgpll clock rate. If we keep the univpll parents from mfg_core_tmp, when setting GPU frequency to 390000000, the common clock framework would switch the parent to univpll, instead of setting mfgpll to 390000000: mfgpll 0 0 0 949999756 univpll 2 2 0 2340000000 univpll_d6 1 1 0 390000000 top_mfg_core_tmp 1 1 0 390000000 mfg_ck_fast_ref 1 1 0 390000000 mfgcfg_bg3d 1 1 0 390000000 This results in failures when subsequent devfreq operations need to switch to other frequencies. So remove univpll from the parent list. This solution is taken from commit 72d38ed720e9 ("clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents") Signed-off-by: Pablo Sun Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240927103005.17605-3-pablo.sun@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers

2024-10-17T19:24:35+00:00

Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg clock and reset controllers. These provide the base clocks and resets on the platform, enough to bring up all essential blocks including PWRAP, MSDC and peripherals (UART, I2C, SPI). Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241017071708.38663-3-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd

clk: mediatek: drop two dead config options

2024-10-09T23:22:49+00:00

Commit 0f471d31e5e8 ("clk: mediatek: Split MT8195 clock drivers and allow module build") adds a number of new COMMON_CLK_MT8195_* config options. Among those, the config options COMMON_CLK_MT8195_AUDSYS and COMMON_CLK_MT8195_MSDC have no reference in the source tree and are not used in the Makefile to include a specific file. Drop the dead config options COMMON_CLK_MT8195_AUDSYS and COMMON_CLK_MT8195_MSDC. Fixes: 0f471d31e5e8 ("clk: mediatek: Split MT8195 clock drivers and allow module build") Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20240927092232.386511-1-lukas.bulwahn@redhat.com Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd