kernel/git/stable/linux.git/drivers/clk/meson, branch linux-4.4.y

clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL

2021-03-03T15:44:18+00:00

[ Upstream commit 2f290b7c67adf6459a17a4c978102af35cd62e4a ] The "rate" parameter in meson_clk_pll_set_rate() contains the new rate. Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try to switch from the new rate to the same rate again. Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20201226121556.975418-2-martin.blumenstingl@googlemail.com Signed-off-by: Sasha Levin

clk: meson: Fix meson_clk_register_clks() signature type mismatch

2016-05-11T09:21:12+00:00

commit bb473593c8099302bfd7befc23de67df907e3a99 upstream. As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Signed-off-by: Andreas Färber Acked-by: Carlo Caione Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: meson8b: Properly include clk.h

2015-07-20T17:53:10+00:00

Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h if it's actually used. Cc: Carlo Caione Signed-off-by: Stephen Boyd

clk: meson: add some error handling in meson_clk_register_cpu()

2015-06-12T21:30:19+00:00

This error handling hopefully isn't needed but it make the static checkers happy. Signed-off-by: Dan Carpenter Acked-by: Carlo Caione Signed-off-by: Stephen Boyd

clk: meson8b: Add support for Meson8b clocks

2015-06-06T00:22:09+00:00

This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs. Signed-off-by: Carlo Caione Signed-off-by: Stephen Boyd

clk: meson: Add support for Meson clock controller

2015-06-06T00:22:08+00:00

This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione Signed-off-by: Stephen Boyd