kernel/git/stable/linux.git/drivers/clk/meson, branch linux-5.5.y

clk: meson: meson8b: make the CCF use the glitch-free mali mux

2020-02-24T07:38:03+00:00

[ Upstream commit 8daeaea99caabe24a0929fac17977ebfb882fa86 ] The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. This fixes a potential hang when changing the GPU frequency at runtime. Fixes: 74e1f2521f16ff ("clk: meson: meson8b: add the GPU clock tree") Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Signed-off-by: Sasha Levin

clk: meson: pll: Fix by 0 division in __pll_params_to_rate()

2020-02-24T07:38:00+00:00

[ Upstream commit d8488a41800d9f5c80bc0d17b9cc2c91b4841464 ] Some meson pll registers can be initialized with 0 as N value, introducing the following division by 0 when computing rate : UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9 division by zero CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400 Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x14/0x20 dump_stack+0xc4/0x100 ubsan_epilogue+0x14/0x68 __ubsan_handle_divrem_overflow+0x98/0xb8 __pll_params_to_rate+0xdc/0x140 meson_clk_pll_recalc_rate+0x278/0x3a0 __clk_register+0x7c8/0xbb0 devm_clk_hw_register+0x54/0xc0 meson_eeclkc_probe+0xf4/0x1a0 platform_drv_probe+0x54/0xd8 really_probe+0x16c/0x438 driver_probe_device+0xb0/0xf0 device_driver_attach+0x94/0xa0 __driver_attach+0x70/0x108 bus_for_each_dev+0xd8/0x128 driver_attach+0x30/0x40 bus_add_driver+0x1b0/0x2d8 driver_register+0xbc/0x1d0 __platform_driver_register+0x78/0x88 axg_driver_init+0x18/0x20 do_one_initcall+0xc8/0x24c kernel_init_freeable+0x2b0/0x344 kernel_init+0x10/0x128 ret_from_fork+0x10/0x18 This checks if N is null before doing the division. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Reviewed-by: Martin Blumenstingl Signed-off-by: Remi Pommarel [jbrunet@baylibre.com: update the comment in above the fix] Signed-off-by: Jerome Brunet Signed-off-by: Sasha Levin

clk: meson: g12a: fix missing uart2 in regmap table

2020-02-14T21:53:06+00:00

commit b1b3f0622a9d52ac19a63619911823c89a4d85a4 upstream. UART2 peripheral is missing from the regmap fixup table of the g12a family clock controller. As it is, any access to this clock would Oops, which is not great. Add the clock to the table to fix the problem. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Reported-by: Dmitry Shmidt Tested-by: Dmitry Shmidt Acked-by: Neil Armstrong Tested-by: Kevin Hilman Signed-off-by: Jerome Brunet Signed-off-by: Greg Kroah-Hartman

clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code

2019-10-14T15:06:27+00:00

Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing Signed-off-by: Jerome Brunet

clk: meson: axg_audio: add sm1 support

2019-10-08T07:29:23+00:00

Add sm1 support the axg audio clock controllers. This new version is indeed derived from the previous generation, as always, adding a few new clocks to the mix. The number of gates now exceeds 32 and do not fit in a single register. Unfortunately, designers chose to introduce the new gate register immediately after the original one, at the beginning of the register space, shifting all the master clock register offsets. The sm1 also introduce a few mux and divider on the top clock path, possibly to lower the peripheral clocks of the audio blocks if necessary. Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: axg-audio: provide clk top signal name

2019-10-08T07:29:23+00:00

The peripheral clock on the sm1 goes through some muxes and dividers before reaching the audio gates. To model that, without repeating our self too much, the "top" clock signal is introduced and will serve as a the parent of the gates. On the axg and g12a, the top clock is just a pass-through to the audio peripheral clock provided by the main controller. Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: axg-audio: prepare sm1 addition

2019-10-08T07:29:22+00:00

Rearrange the macro definition of the clocks of the axg-audio controller. Also, the sm1 variant will feature tiny modification of different blocks in this controller. Because of that, we need to fallback to the old way of defining parent for some of the clocks, using signal name. Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: axg-audio: fix regmap last register

2019-10-08T07:29:21+00:00

Since the addition of the g12a, the last register is AUDIO_CLK_SPDIFOUT_B_CTRL. Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support") Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: axg-audio: remove useless defines

2019-10-08T07:29:21+00:00

Defining the number of each input type is no longer necessary since we are not using the clk-input hack anymore Fixes: 282420eed23f ("clk: meson: axg-audio: migrate to the new parent description method") Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes

2019-10-01T12:51:15+00:00

When setting the 100MHz, 500MHz, 666MHz and 1GHz rate for CPU clocks, CCF will use the SYS_PLL to handle these frequencies, but: - using FIXED_PLL derived FCLK_DIV2/DIV3 clocks is more precise - the Amlogic G12A/G12B/SM1 Suspend handling in firmware doesn't handle entering suspend using SYS_PLL for these frequencies Adding CLK_MUX_ROUND_CLOSEST on all the muxes of the non-SYS_PLL cpu clock tree helps CCF always selecting the FCLK_DIV2/DIV3 as source for these frequencies. Fixes: ffae8475b90c ("clk: meson: g12a: add notifiers to handle cpu clock change") Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet