kernel/git/stable/linux.git/drivers/clk/qcom, branch linux-6.4.y

clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock

2023-09-13T07:48:22+00:00

[ Upstream commit 06d71fa10f2e507444c6759328a6c19d38eab788 ] gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-qdu1000: Fix clkref clocks handling

2023-09-13T07:48:22+00:00

[ Upstream commit 2524dae5cd453ca39e8ba1b95c2755a8a2d94059 ] Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling

2023-09-13T07:48:22+00:00

[ Upstream commit b311f5d3c4749259043a9a458a8db07915210142 ] Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs

2023-09-13T07:48:22+00:00

[ Upstream commit a27ac3806b0a0e6954fb5967223b8635242e5b8f ] Use the floor ops to prevent warnings like this at suspend exit and boot: mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450") Signed-off-by: Konrad Dybcio Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-sm6350: Fix gcc_sdcc2_apps_clk_src

2023-09-13T07:48:21+00:00

[ Upstream commit df04d166d1f346dbf740bbea64a3bed3e7f14c8d ] GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230804-sm6350-sdcc2-v1-1-3d946927d37d@fairphone.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: reset: Use the correct type of sleep/delay based on length

2023-09-13T07:48:21+00:00

[ Upstream commit 181b66ee7cdd824797fc99b53bec29cf5630a04f ] Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b6781 ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-qcom_reset-v3-1-5958facd5db2@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-sm8250: Fix gcc_sdcc2_apps_clk_src

2023-09-13T07:48:21+00:00

[ Upstream commit 783cb693828ce487cf0bc6ad16cbcf2caae6f8d9 ] GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Patrick Whewell Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20230802210359.408-1-patrick.whewell@sightlineapplications.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-sc7180: Fix up gcc_sdcc2_apps_clk_src

2023-09-13T07:48:21+00:00

[ Upstream commit fd0b5ba87ad5709f0fd3d2bc4b7870494a75f96a ] Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: David Wronek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230723190725.1619193-2-davidwronek@gmail.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCs

2023-09-13T07:48:20+00:00

[ Upstream commit 20e1d75bc043c5ec1fd8f5169fde17db89eb11c3 ] The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230725-topic-8280_dispcc_gdsc-v1-1-236590060531@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gcc-sm7150: Add CLK_OPS_PARENT_ENABLE to sdcc2 rcg

2023-09-13T07:48:20+00:00

[ Upstream commit ff19022b9112d6bbd7c117c83e944cb21b438e91 ] Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: a808d58ddf29 ("clk: qcom: Add Global Clock Controller (GCC) driver for SM7150") Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230630191944.20282-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin