kernel/git/stable/linux.git/drivers/clk/rockchip, branch linux-3.18.y

clk: rockchip: fix deadlock possibility in cpuclk

2018-11-10T15:39:17+00:00

[ Upstream commit a5e1baf7dca10f8cf945394034013260297bc416 ] Lockdep reported a possible deadlock between the cpuclk lock and for example the i2c driver. CPU0 CPU1 ---- ---- lock(clk_lock); local_irq_disable(); lock(&(&i2c->lock)->rlock); lock(clk_lock); lock(&(&i2c->lock)->rlock); *** DEADLOCK *** The generic clock-types of the core ccf already use spin_lock_irqsave when touching clock registers, so do the same for the cpuclk. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Signed-off-by: Michael Turquette [mturquette@linaro.org: removed initialization of "flags"] Signed-off-by: Sasha Levin

clk: rockchip: free memory in error cases when registering clock branches

2016-07-12T12:48:01+00:00

[ Upstream commit 2467b6745e0ae9c6cdccff24c4cceeb14b1cce3f ] Add free memeory if rockchip_clk_register_branch fails. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...") Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

2016-04-18T12:49:15+00:00

[ Upstream commit 3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a ] Now that the rockchip clock subsystem does clock gating with GPIO banks, these are no longer enabled once during probe and no longer stay enabled for eternity. When all these clocks are disabled, the parent clock pclk_peri might be disabled too, as no other child claims it. So, we need to add pclk_peri to the critical clocks. Signed-off-by: Romain Perier Tested-by: Michael Niewoehner Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks

2016-04-18T12:49:15+00:00

[ Upstream commit 1166160ab531198f7abc773992c0e04d0f9b7600 ] pclk_cpu needs to keep running because it is needed for devices like the act8865 regulator but with the recent gpio clock handling this is not always the case anymore. So add it to the list of critical clocks. Signed-off-by: Michael Niewoehner Reviewed-by: Heiko Stuebner Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: rockchip: fix rk3066 pll lock bit location

2015-01-27T16:29:38+00:00

commit 12551f0239b50c88352e3292dd7703382addbf5e upstream. The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll. The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table. Fix this by defining separate pll definitions for rk3066 with the correct locking indices. Signed-off-by: Heiko Stuebner Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks") Tested-by: FUKAUMI Naoki Signed-off-by: Greg Kroah-Hartman

clk: rockchip: fix rk3288 cpuclk core dividers

2015-01-27T16:29:38+00:00

commit 9880d4277f6aab6b21404c824f9d9c652ba518ac upstream. Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by: Sonny Rao Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Signed-off-by: Greg Kroah-Hartman

clk-divider: Fix READ_ONLY when divider > 1

2014-11-17T19:13:52+00:00

Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the recalc_rate() and round_rate() clock callbacks to be omitted. However using this flag has the unfortunate side effect of causing the clock recalculation code when a clock rate change is attempted to always treat it as a pass-through clock, i.e. with a fixed divide of 1, which may not be the case. Child clock rates are then recalculated using the wrong parent rate. Therefore instead of dropping the recalc_rate() and round_rate() callbacks, alter clk_divider_bestdiv() to always report the current divider as the best divider so that it is never altered. For me the read only clock was the system clock, which divided the PLL rate by 2, from which both the UART and the SPI clocks were divided. Initial setting of the UART rate set it correctly, but when the SPI clock was set, the other child clocks were miscalculated. The UART clock was recalculated using the PLL rate as the parent rate, resulting in a UART new_rate of double what it should be, and a UART which spewed forth garbage when the rate changes were propagated. Signed-off-by: James Hogan Cc: Thomas Abraham Cc: Tomasz Figa Cc: Max Schwarz Cc: # v3.16+ Acked-by: Haojian Zhuang Signed-off-by: Michael Turquette

clk: rockchip: add restart handler

2014-10-01T12:11:42+00:00

Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: Heiko Stuebner Signed-off-by: Guenter Roeck

clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate

2014-10-01T08:55:13+00:00

The relation of i2s nodes as follows: i2s_src 0 0 594000000 0 i2s_frac 0 0 11289600 0 i2s_pre 0 0 11289600 0 sclk_i2s0 0 0 11289600 0 i2s0_clkout 0 0 11289600 0 hclk_i2s0 1 1 99000000 0 sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". Tested on rk3288 board using max98090, with command "aplay " Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Signed-off-by: Jianqun Signed-off-by: Heiko Stuebner

clk: rockchip: switch to using the new cpuclk type for armclk

2014-09-27T15:57:46+00:00

This adds the necessary soc-specific divider values and switches the armclk to use the newly introduced cpuclk type. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Tested-by: Doug Anderson