kernel/git/stable/linux.git/drivers/clk/sunxi, branch linux-3.18.y

sunxi: clk: Set sun6i-pll1 n_start = 1

2015-03-24T01:02:47+00:00

commit 76820fcf7aa5a418b69cb7bed31b62d1feb1d6ad upstream. For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set for sun6i pll6, but was missing for pll1, this commit fixes this. Cc: Chen-Yu Tsai Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Signed-off-by: Greg Kroah-Hartman

Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

2014-09-27T19:52:33+00:00

Allwinner Clocks Additions for 3.18 The most important part of this serie is the addition of the phase API to handle the MMC clocks in the Allwinner SoCs. Apart from that, the A23 gained a new mbus driver, and there's a fix for a incorrect divider table on the APB0 clock.

clk: sunxi: Add sun8i MBUS clock support

2014-09-27T07:05:43+00:00

The MBUS clock on sun8i is slightly different from the old mod0 clocks. The divider is 3 bits wider, while also needing a divider table for the higher 4 values, which all set the same divider. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: mod0: Introduce MMC proper phase handling

2014-09-27T06:58:04+00:00

The MMC clock we thought we had until now are actually not one but three different clocks. The main one is unchanged, and will have three outputs: - The clock fed into the MMC - a sample and output clocks, to deal with when should we output/sample data to/from the MMC bus The phase control we had are actually controlling the two latter clocks, but the main MMC one is unchanged. We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase shift, and the other values being the number of periods from the MMC parent clock to outphase the clock of. Signed-off-by: Maxime Ripard Acked-by: Hans de Goede

clk: sunxi: Move mbus to mod0 file

2014-09-27T06:58:03+00:00

Move the MBUS clock to the module clocks file. It's pretty trivial, but still requires to enable the clocks to make sure it won't get disabled. Signed-off-by: Maxime Ripard Acked-by: Hans de Goede

clk: sunxi: Move mod0 clock to a file of its own

2014-09-27T06:58:03+00:00

Since we know have the ability to declare factors clock outside of clk-sunxi, create a new mod0 driver to deal with the mod0 clocks. Signed-off-by: Maxime Ripard Acked-by: Hans de Goede

clk: sunxi: Introduce mbus compatible

2014-09-27T06:58:02+00:00

Even though the mbus clock is a regular module clock, given its nature, it needs to be enabled all the time. Introduce a new compatible, to differentiate it from the other module clocks. Signed-off-by: Maxime Ripard Acked-by: Hans de Goede

clk: sunxi: factors: Invert the probing logic

2014-09-27T06:58:01+00:00

Until now, the factors clock probing was done directly by sunxi_init_clocks, with the factors registration being called directly with the clocks data passed as an argument. This approch has shown its limits when we added more clocks, since we couldn't really split code with such a logic in smaller files, and led to a huge file having all the clocks. Introduce an intermediate probing function, so that factor clocks will be able to directly be called by CLK_OF_DECLARE, which will in turn ease the split into several files. Signed-off-by: Maxime Ripard Acked-by: Hans de Goede

clk: Remove .owner field for driver

2014-09-26T00:43:31+00:00

There is no need to init .owner field. Based on the patch from Peter Griffin "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Kiran Padwal Signed-off-by: Mike Turquette

clk: sunxi: add correct divider table for sun4i-apb0 clock

2014-09-13T08:07:24+00:00

The sun4i-apb0 clock, as found on all platforms using it, is a power-of-two-based divider clock, with a special divider of 2 for value 0. This was causing the clock framework to incorrectly calculate the clock rate for apb1 and related modules on sun6i and sun8i. On sun[4/5/7]i, u-boot SPL configures the divider with value 1 for /2 divider, so no suprises there. This patch adds a proper divider table for it, so the correct clock rate can be calculated. Signed-off-by: Chen-Yu Tsai Acked-by: Emilio López Signed-off-by: Maxime Ripard