kernel/git/stable/linux.git/drivers/clk/sunxi, branch linux-4.7.y

clk: sunxi: remove unused variable

2016-06-16T07:18:29+00:00

The only use of the local num_parents variable was remove, so we now get a warning: drivers/clk/sunxi/clk-sun4i-tcon-ch1.c: In function 'tcon_ch1_get_parent': drivers/clk/sunxi/clk-sun4i-tcon-ch1.c:82:6: error: unused variable 'num_parents' [-Werror=unused-variable] This removes the variable. Signed-off-by: Arnd Bergmann Fixes: 4de2d58bc973 ("clk: sunxi: tcon-ch1: Do not return a negative error in get_parent") Signed-off-by: Maxime Ripard

clk: sunxi: display: Add per-clock flags

2016-06-10T09:49:47+00:00

The TCON channel 0 clock that is the parent clock of our pixel clock is expected to change its rate depending on the resolution we want to output in our display engine. However, since it's only a mux, the only way it can do that is by changing its parents rate. Allow to give flags in our display clocks description, and add the CLK_SET_RATE_PARENT flag for the TCON channel 0 flag. Fixes: a3b4956ee6d9 ("clk: sunxi: display: Add per-clock flags") Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: tcon-ch1: Do not return a negative error in get_parent

2016-06-10T09:49:15+00:00

get_parent is supposed to return an unsigned 8 bit integer, so returning -EINVAL is a bad idea. Remove it. Reported-by: Dan Carpenter Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Add display and TCON0 clocks driver

2016-05-12T21:47:52+00:00

The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: Maxime Ripard Acked-by: Rob Herring [sboyd@codeaurora.org: Silence variable sized array warning] Signed-off-by: Stephen Boyd

Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

2016-05-03T00:03:08+00:00

Pull Allwinner clock driver updates from Maxime Ripard: As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. * tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add TCON channel1 clock clk: sunxi: Add PLL3 clock dt-bindings: clk: sun5i: add DRAM gates compatible clk: sunxi: Use resource_size clk: sunxi: Add sun6i/8i display support clk: sunxi: mod1 clock should modify it's parent

clk: sunxi: Let divs clocks read the base factor clock name from devicetree

2016-04-25T08:57:45+00:00

Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit makes the divs setup function try to get a name from clock-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. [Andre: Make temporary name allocation dynamic.] Signed-off-by: Jens Kuske Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard

clk: sunxi: Add TCON channel1 clock

2016-04-21T22:29:24+00:00

The TCON is a controller generating the timings to output videos signals, acting like both a CRTC and an encoder. It has two channels depending on the output, each channel being driven by its own clock (and own clock controller). Add a driver for the channel 1 clock. Signed-off-by: Maxime Ripard Acked-by: Rob Herring Acked-by: Stephen Boyd

clk: sunxi: Add PLL3 clock

2016-04-21T22:29:23+00:00

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard

clk: sunxi: Use resource_size

2016-04-21T22:29:22+00:00

Use the function resource_size instaed of explicit computation. Problem found using Coccinelle. Signed-off-by: Vaishali Thakkar Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Add sun6i/8i display support

2016-04-21T22:29:22+00:00

Add the clock type which is used by the sun6i/8i families for video display. Signed-off-by: Jean-Francois Moine Acked-by: Rob Herring Signed-off-by: Maxime Ripard