kernel/git/stable/linux.git/drivers/clk/tegra, branch linux-4.0.y

clk: tegra: Use the proper parent for plld_dsi

2015-05-06T20:03:58+00:00

commit c1d676cec572544616273d5853cb7cc38fbaa62b upstream. The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman

clk: tegra: Register the proper number of resets

2015-05-06T20:03:58+00:00

commit 5e43e259171e1eee8bc074d9c44be434e685087b upstream. The number of resets controls is 32 times the number of peripheral register banks rather than 32 times the number of clocks. This reduces (drastically) the number of reset controls registered from 10080 (315 clocks * 32) to 224 (6 peripheral register banks * 32). This also fixes a potential crash because trying to use any of the excess reset controls (224-10079) would have caused accesses beyond the array bounds of the peripheral register banks definition array. Cc: Peter De Schrijver Cc: Prashant Gaikwad Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver") Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman

clk: Replace explicit clk assignment with __clk_hw_set_clk

2015-02-18T17:40:11+00:00

The change in the clk API to return a per-user clock instance, moved the clock state to struct clk_core so now the struct clk_hw .core field is used instead of .clk for most operations. So for hardware clocks that needs to share the same clock state, both the .core and .clk pointers have to be assigned but currently only the .clk is set. This leads to NULL pointer dereference when the operations try to access the hw clock .core. For example, the composite clock rate and mux components didn't have a .core set which leads to this error: Unable to handle kernel NULL pointer dereference at virtual address 00000034 pgd = c0004000 [00000034] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) task: ee480000 ti: ee488000 task.ti: ee488000 PC is at clk_mux_determine_rate_flags+0x14/0x19c LR is at __clk_mux_determine_rate+0x24/0x2c pc : [] lr : [] psr: a0000113 sp : ee489ce8 ip : ee489d84 fp : ee489d84 r10: 0000005c r9 : 00000001 r8 : 016e3600 r7 : 00000000 r6 : 00000000 r5 : ee442200 r4 : ee440c98 r3 : ffffffff r2 : 00000000 r1 : 016e3600 r0 : ee440c98 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 4000406a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xee488210) Stack: (0xee489ce8 to 0xee48a000) 9ce0: 00000000 ffffffff 60000113 ee440c98 ee442200 00000000 9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84 9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea 9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000 9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84 9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff 9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4 9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700 9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64 9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54 9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0 9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010 9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c 9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000 9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40 9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4 9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944 9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000 9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec 9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424 9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006 9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000 9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [] (clk_mux_determine_rate_flags) from [] (__clk_mux_determine_rate+0x24/0x2c) [] (__clk_mux_determine_rate) from [] (clk_composite_determine_rate+0xbc/0x238) [] (clk_composite_determine_rate) from [] (clk_core_round_rate_nolock+0x5c/0x9c) [] (clk_core_round_rate_nolock) from [] (__clk_round_rate+0x38/0x40) [] (__clk_round_rate) from [] (clk_round_rate+0x20/0x38) [] (clk_round_rate) from [] (max98090_dai_set_sysclk+0x34/0x118) [] (max98090_dai_set_sysclk) from [] (snd_soc_dai_set_sysclk+0x38/0x80) [] (snd_soc_dai_set_sysclk) from [] (snow_late_probe+0x24/0x48) [] (snow_late_probe) from [] (snd_soc_register_card+0xf04/0x1070) [] (snd_soc_register_card) from [] (devm_snd_soc_register_card+0x30/0x64) [] (devm_snd_soc_register_card) from [] (snow_probe+0x68/0xcc) [] (snow_probe) from [] (platform_drv_probe+0x48/0x98) [] (platform_drv_probe) from [] (driver_probe_device+0x114/0x234) [] (driver_probe_device) from [] (__driver_attach+0x8c/0x90) [] (__driver_attach) from [] (bus_for_each_dev+0x54/0x88) [] (bus_for_each_dev) from [] (bus_add_driver+0xd8/0x1cc) [] (bus_add_driver) from [] (driver_register+0x78/0xf4) [] (driver_register) from [] (do_one_initcall+0x80/0x1d0) [] (do_one_initcall) from [] (kernel_init_freeable+0x10c/0x1d8) [] (kernel_init_freeable) from [] (kernel_init+0x8/0xe4) [] (kernel_init) from [] (ret_from_fork+0x14/0x34) Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034) The changes were made using the following cocinelle semantic patch: @i@ @@ @depends on i@ identifier dst; @@ - dst->clk = hw->clk; + __clk_hw_set_clk(dst, hw); @depends on i@ identifier dst; @@ - dst->hw.clk = hw->clk; + __clk_hw_set_clk(&dst->hw, hw); Fixes: 035a61c314eb3 ("clk: Make clk API return per-user struct clk instances") Signed-off-by: Javier Martinez Canillas Reviewed-by: Stephen Boyd Signed-off-by: Michael Turquette

clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

2015-02-02T14:22:34+00:00

PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver Signed-off-by: Mark Zhang

clk: tegra: Add support for the Tegra132 CAR IP block

2015-02-02T13:47:53+00:00

Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences. Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support. This patch is based on several patches from others: 1. a patch from Peter De Schrijver: http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html 2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and 3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132"). Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Peter De Schrijver Cc: Allen Martin Cc: Prashant Gaikwad Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot Cc: Bill Huang Cc: Mike Turquette Cc: Stephen Boyd

clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

2015-02-02T13:47:28+00:00

tegra_clocks_apply_init_table() needs to be called after the udelay loop has been calibrated (see commit 441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer application of init table") for why that is). On existing Tegra SoCs this was done by calling tegra_clocks_apply_init_table() from tegra_dt_init(). To make this also work on ARM64, we need to change this into an initcall. tegra_dt_init() is called from customize_machine which is an arch_initcall. Therefore this should also work on existing 32bit Tegra SoCs. Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and Tegra132. Signed-off-by: Peter De Schrijver [paul@pwsan.com: tweaked the commit message] Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Thierry Reding Cc: Prashant Gaikwad Cc: Mike Turquette Cc: Stephen Boyd Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot

clk: tegra: Fix order of arguments in WARN

2015-02-02T13:47:04+00:00

As previously the names of the present clock and its parent were swapped. Signed-off-by: Tomeu Vizoso Signed-off-by: Peter De Schrijver

clk: tegra124: Add init data for dsi lp clocks

2015-02-02T13:46:34+00:00

Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul Signed-off-by: Peter De Schrijver

clk: tegra: SDMMC controllers are on APB

2015-02-02T13:46:14+00:00

Since the SDMMC controller registers are accessed via the APB, the APB must be flushed before gating the SDMMC clocks to prevent register accesses to the SDMMC controllers after their clocks are gated. Signed-off-by: Andrew Bresticker Signed-off-by: Peter De Schrijver

clk: tegra: Implement memory-controller clock

2014-11-26T08:43:23+00:00

The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso Acked-by: Mike Turquette Signed-off-by: Thierry Reding