kernel/git/stable/linux.git/drivers/counter/Kconfig, branch linux-6.4.y

counter: Add Renesas RZ/G2L MTU3a counter driver

2023-04-26T10:40:35+00:00

Add RZ/G2L MTU3a counter driver. This IP supports the following phase counting modes on MTU1 and MTU2 channels 1) 16-bit phase counting modes on MTU1 and MTU2 channels. 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. This patch adds 3 counter value channels. count0: 16-bit phase counter value channel on MTU1 count1: 16-bit phase counter value channel on MTU2 count2: 32-bit phase counter value channel by cascading MTU1 and MTU2 channels. The external input phase clock pin for the counter value channels are as follows: count0: "MTCLKA-MTCLKB" count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" Use the sysfs variable "external_input_phase_clock_select" to select the external input phase clock pin and "cascade_counts_enable" to enable/ disable cascading of channels. Signed-off-by: Biju Das Reviewed-by: William Breathitt Gray Acked-by: William Breathitt Gray Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20230330111632.169434-5-biju.das.jz@bp.renesas.com

counter: fix dependency references for config MICROCHIP_TCB_CAPTURE

2023-01-18T14:59:58+00:00

Commit dfeef15e73ca ("counter: microchip-tcp-capture: Add appropriate arch deps for TCP driver") intends to add appropriate dependencies for the config MICROCHIP_TCB_CAPTURE. It however prefixes the intended configs with CONFIG, but in Kconfig files in contrast to source files, the configs are referenced to without prefixing them with CONFIG. Fix the dependency references due to this minor misconception. Fixes: dfeef15e73ca ("counter: microchip-tcp-capture: Add appropriate arch deps for TCP driver") Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20230118074659.5909-1-lukas.bulwahn@gmail.com/ Signed-off-by: William Breathitt Gray

counter: microchip-tcp-capture: Add appropriate arch deps for TCP driver

2023-01-13T20:05:56+00:00

Add the CONFIG_SOC_AT91SAM9 and CONFIG_SOC_SAM_V7 deps for the Microchip SoCs that support this IP block/driver plus compile time testing. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20230108074750.443705-4-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray

counter: ftm-quaddec: Depend on the Layerscape SoC

2023-01-13T20:05:41+00:00

At the moment only the Freescale LS1021A is the only HW that supports this IP block so add an appropriate dependency and compile test. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20230108074750.443705-3-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray

counter: intel-qep: Depend on X86

2023-01-13T20:05:23+00:00

Limit the Intel counter driver to X86, it doesn't make sense to build it for all arches if the counter subsystem is enabled. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20230108074750.443705-2-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray

counter: Sort the Kconfig entries alphabetically

2023-01-13T20:04:20+00:00

Sort the Kconfig menu alphabetically to make it easier to read as the list grows larger. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20230108074750.443705-1-pbrobinson@gmail.com/ Signed-off-by: William Breathitt Gray

counter: ti-ecap-capture: capture driver support for ECAP

2022-09-30T12:32:35+00:00

ECAP hardware on TI AM62x SoC supports capture feature. It can be used to timestamp events (falling/rising edges) detected on input signal. This commit adds capture driver support for ECAP hardware on AM62x SoC. In the ECAP hardware, capture pin can also be configured to be in PWM mode. Current implementation only supports capture operating mode. Hardware also supports timebase sync between multiple instances, but this driver supports simple independent capture functionality. Signed-off-by: Julien Panis Link: https://lore.kernel.org/r/20220923142437.271328-4-jpanis@baylibre.com/ Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/25644ce1f2fd15d116977770ede20e024f658513.1664318353.git.william.gray@linaro.org Signed-off-by: Greg Kroah-Hartman

counter: 104-quad-8: Add COMPILE_TEST depends

2022-03-18T13:04:30+00:00

104_QUAD_8 depends on X86, but compiles fine on ARCH=arm. This patch adds support for COMPILE_TEST which is useful for compile testing code changes to the driver and Counter subsystem. Link: https://lore.kernel.org/r/20220105094137.259111-1-vilhelm.gray@gmail.com Cc: Syed Nayyar Waris Suggested-by: Uwe Kleine-König Acked-by: Uwe Kleine-König Acked-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/3917721e792d362ee108b2f12cd2223675449d05.1647373009.git.vilhelm.gray@gmail.com Signed-off-by: Greg Kroah-Hartman

counter: 104-quad-8: Add IRQ support for the ACCES 104-QUAD-8

2021-10-17T09:55:55+00:00

The LSI/CSI LS7266R1 chip provides programmable output via the FLG pins. When interrupts are enabled on the ACCES 104-QUAD-8, they occur whenever FLG1 is active. Four functions are available for the FLG1 signal: Carry, Compare, Carry-Borrow, and Index. Carry: Interrupt generated on active low Carry signal. Carry signal toggles every time the respective channel's counter overflows. Compare: Interrupt generated on active low Compare signal. Compare signal toggles every time respective channel's preset register is equal to the respective channel's counter. Carry-Borrow: Interrupt generated on active low Carry signal and active low Borrow signal. Carry signal toggles every time the respective channel's counter overflows. Borrow signal toggles every time the respective channel's counter underflows. Index: Interrupt generated on active high Index signal. These four functions correspond respectivefly to the following four Counter event types: COUNTER_EVENT_OVERFLOW, COUNTER_EVENT_THRESHOLD, COUNTER_EVENT_OVERFLOW_UNDERFLOW, and COUNTER_EVENT_INDEX. Interrupts push Counter events to event channel X, where 'X' is the respective channel whose FLG1 activated. This patch adds IRQ support for the ACCES 104-QUAD-8. The interrupt line numbers for the devices may be configured via the irq array module parameter. Acked-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/e3a28e100840e3a336fa93fce77445f0e9d9a674.1632884256.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron

counter: Add support for Intel Quadrature Encoder Peripheral

2021-06-03T17:24:14+00:00

Add support for Intel Quadrature Encoder Peripheral found on Intel Elkhart Lake platform. Initial implementation was done by Felipe Balbi while he was working at Intel with later changes from Raymond Tan and me. Co-developed-by: Felipe Balbi (Intel) Signed-off-by: Felipe Balbi (Intel) Co-developed-by: Raymond Tan Signed-off-by: Raymond Tan Signed-off-by: Jarkko Nikula Acked-by: William Breathitt Gray Link: https://lore.kernel.org/r/20210602113259.158674-1-jarkko.nikula@linux.intel.com Signed-off-by: Jonathan Cameron