<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/drivers/edac, branch linux-6.17.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=linux-6.17.y</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=linux-6.17.y'/>
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<updated>2025-11-24T09:37:47+00:00</updated>
<entry>
<title>EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection</title>
<updated>2025-11-24T09:37:47+00:00</updated>
<author>
<name>Niravkumar L Rabara</name>
<email>niravkumarlaxmidas.rabara@altera.com</email>
</author>
<published>2025-11-11T08:13:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=2a2b4b0277d35316d88a34101fd3446b6465cac7'/>
<id>urn:sha1:2a2b4b0277d35316d88a34101fd3446b6465cac7</id>
<content type='text'>
commit 281326be67252ac5794d1383f67526606b1d6b13 upstream.

The current single-bit error injection mechanism flips bits directly in ECC RAM
by performing write and read operations. When the ECC RAM is actively used by
the Ethernet or USB controller, this approach sometimes trigger a false
double-bit error.

Switch both Ethernet and USB EDAC devices to use the INTTEST register
(altr_edac_a10_device_inject_fops) for single-bit error injection, similar to
the existing double-bit error injection method.

Fixes: 064acbd4f4ab ("EDAC, altera: Add Stratix10 peripheral support")
Signed-off-by: Niravkumar L Rabara &lt;niravkumarlaxmidas.rabara@altera.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Acked-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111081333.1279635-1-niravkumarlaxmidas.rabara@altera.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>EDAC/altera: Handle OCRAM ECC enable after warm reset</title>
<updated>2025-11-24T09:37:47+00:00</updated>
<author>
<name>Niravkumar L Rabara</name>
<email>niravkumarlaxmidas.rabara@altera.com</email>
</author>
<published>2025-11-11T08:08:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f2937825ca7c1ab324395062f77d8f1c71736e4b'/>
<id>urn:sha1:f2937825ca7c1ab324395062f77d8f1c71736e4b</id>
<content type='text'>
commit fd3ecda38fe0cb713d167b5477d25f6b350f0514 upstream.

The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to preserve data,
while the control and status registers are reset to their default values. As
a result, ECC must be explicitly re-enabled after a warm reset.

Fixes: 17e47dc6db4f ("EDAC/altera: Add Stratix10 OCRAM ECC support")
Signed-off-by: Niravkumar L Rabara &lt;niravkumarlaxmidas.rabara@altera.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Acked-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>EDAC/mc_sysfs: Increase legacy channel support to 16</title>
<updated>2025-11-02T13:18:04+00:00</updated>
<author>
<name>Avadhut Naik</name>
<email>avadhut.naik@amd.com</email>
</author>
<published>2025-09-16T20:30:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=47f3af1a9bd7033a29c6cc13214200665f53be00'/>
<id>urn:sha1:47f3af1a9bd7033a29c6cc13214200665f53be00</id>
<content type='text'>
[ Upstream commit 6e1c2c6c2c40ce99e0d2633b212f43c702c1a002 ]

Newer AMD systems can support up to 16 channels per EDAC "mc" device.
These are detected by the EDAC module running on the device, and the
current EDAC interface is appropriately enumerated.

The legacy EDAC sysfs interface however, provides device attributes for
channels 0 through 11 only. Consequently, the last four channels, 12
through 15, will not be enumerated and will not be visible through the
legacy sysfs interface.

Add additional device attributes to ensure that all 16 channels, if
present, are enumerated by and visible through the legacy EDAC sysfs
interface.

Signed-off-by: Avadhut Naik &lt;avadhut.naik@amd.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Link: https://lore.kernel.org/20250916203242.1281036-1-avadhut.naik@amd.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>EDAC: Fix wrong executable file modes for C source files</title>
<updated>2025-11-02T13:18:03+00:00</updated>
<author>
<name>Kuan-Wei Chiu</name>
<email>visitorckw@gmail.com</email>
</author>
<published>2025-08-28T19:19:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a2c98fc5184dd43a0d188d17b75c49c393f35b36'/>
<id>urn:sha1:a2c98fc5184dd43a0d188d17b75c49c393f35b36</id>
<content type='text'>
[ Upstream commit 71965cae7db394ff5ba3b2d2befe4e136ceec268 ]

Three EDAC source files were mistakenly marked as executable when adding the
EDAC scrub controls.

These are plain C source files and should not carry the executable bit.
Correcting their modes follows the principle of least privilege and avoids
unnecessary execute permissions in the repository.

  [ bp: Massage commit message. ]

Signed-off-by: Kuan-Wei Chiu &lt;visitorckw@gmail.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Link: https://lore.kernel.org/20250828191954.903125-1-visitorckw@gmail.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>EDAC/ie31200: Add two more Intel Alder Lake-S SoCs for EDAC support</title>
<updated>2025-11-02T13:18:03+00:00</updated>
<author>
<name>Kyle Manna</name>
<email>kyle@kylemanna.com</email>
</author>
<published>2025-08-19T16:17:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=cc81ee432884d2d68d30684ef3e1b3f1c7dfa284'/>
<id>urn:sha1:cc81ee432884d2d68d30684ef3e1b3f1c7dfa284</id>
<content type='text'>
[ Upstream commit 71b69f817e91b588030d7d47ddbdc4857a92eb4e ]

Host Device IDs (DID0) correspond to:
* Intel Core i7-12700K
* Intel Core i5-12600K

See documentation:
* 12th Generation Intel® Core™ Processors Datasheet
    * Volume 1 of 2, Doc. No.: 655258, Rev.: 011
    * https://edc.intel.com/output/DownloadPdfDocument?id=8297 (PDF)

Signed-off-by: Kyle Manna &lt;kyle@kylemanna.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Reviewed-by: Qiuxu Zhuo &lt;qiuxu.zhuo@intel.com&gt;
Link: https://lore.kernel.org/r/20250819161739.3241152-1-kyle@kylemanna.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller</title>
<updated>2025-10-15T10:03:17+00:00</updated>
<author>
<name>Qiuxu Zhuo</name>
<email>qiuxu.zhuo@intel.com</email>
</author>
<published>2025-08-06T06:57:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=c20da24272f1ac79e9f9083bba577d049cd02bbb'/>
<id>urn:sha1:c20da24272f1ac79e9f9083bba577d049cd02bbb</id>
<content type='text'>
[ Upstream commit 2e6fe1bbefd9c059c3787d1c620fe67343a94dff ]

When loading the i10nm_edac driver on some Intel Granite Rapids servers,
a call trace may appear as follows:

  UBSAN: shift-out-of-bounds in drivers/edac/skx_common.c:453:16
  shift exponent -66 is negative
  ...
  __ubsan_handle_shift_out_of_bounds+0x1e3/0x390
  skx_get_dimm_info.cold+0x47/0xd40 [skx_edac_common]
  i10nm_get_dimm_config+0x23e/0x390 [i10nm_edac]
  skx_register_mci+0x159/0x220 [skx_edac_common]
  i10nm_init+0xcb0/0x1ff0 [i10nm_edac]
  ...

This occurs because some BIOS may disable a memory controller if there
aren't any memory DIMMs populated on this memory controller. The DIMMMTR
register of this disabled memory controller contains the invalid value
~0, resulting in the call trace above.

Fix this call trace by skipping DIMM enumeration on a disabled memory
controller.

Fixes: ba987eaaabf9 ("EDAC/i10nm: Add Intel Granite Rapids server support")
Reported-by: Jose Jesus Ambriz Meza &lt;jose.jesus.ambriz.meza@intel.com&gt;
Reported-by: Chia-Lin Kao (AceLan) &lt;acelan.kao@canonical.com&gt;
Closes: https://lore.kernel.org/all/20250730063155.2612379-1-acelan.kao@canonical.com/
Signed-off-by: Qiuxu Zhuo &lt;qiuxu.zhuo@intel.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Tested-by: Chia-Lin Kao (AceLan) &lt;acelan.kao@canonical.com&gt;
Link: https://lore.kernel.org/r/20250806065707.3533345-1-qiuxu.zhuo@intel.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>EDAC/altera: Delete an inappropriate dma_free_coherent() call</title>
<updated>2025-08-25T11:56:16+00:00</updated>
<author>
<name>Salah Triki</name>
<email>salah.triki@gmail.com</email>
</author>
<published>2025-07-31T03:15:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=ff2a66d21fd2364ed9396d151115eec59612b200'/>
<id>urn:sha1:ff2a66d21fd2364ed9396d151115eec59612b200</id>
<content type='text'>
dma_free_coherent() must only be called if the corresponding
dma_alloc_coherent() call has succeeded. Calling it when the allocation fails
leads to undefined behavior.

Delete the wrong call.

  [ bp: Massage commit message. ]

Fixes: 71bcada88b0f3 ("edac: altera: Add Altera SDRAM EDAC support")
Signed-off-by: Salah Triki &lt;salah.triki@gmail.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Acked-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/aIrfzzqh4IzYtDVC@pc
</content>
</entry>
<entry>
<title>Merge tag 'edac_updates_for_v6.17_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras</title>
<updated>2025-07-29T23:30:38+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-07-29T23:30:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d7223aed30cd77be31dabd635e709828f3255366'/>
<id>urn:sha1:d7223aed30cd77be31dabd635e709828f3255366</id>
<content type='text'>
Pull EDAC updates from Borislav Petkov:

 - i10nm:
     - switch to using scnprintf()
     - Add Granite Rapids-D support

 - synopsys: Make sure ECC error and counter registers are cleared
   during init/probing to avoid reporting stale errors

 - igen6: Add Wildcat Lake SoCs support

 - Make sure scrub features sysfs attributes are initialized properly

 - Allocate memory repair sysfs attributes statically to reduce stack
   usage

 - Fix DIMM module size computation for DIMMs with total capacity which
   is a non power-of-two number, in amd64_edac

 - Do not be too dramatic when reporting disabled memory controllers in
   igen6_edac

 - Add support to ie31200_edac for the following SoCs:
     - Core i5-14[67]00
     - Bartless Lake-S SoCs
     - Raptor Lake-HX

* tag 'edac_updates_for_v6.17_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/{skx_common,i10nm}: Use scnprintf() for safer buffer handling
  EDAC/synopsys: Clear the ECC counters on init
  EDAC/ie31200: Add Intel Raptor Lake-HX SoCs support
  EDAC/igen6: Add Intel Wildcat Lake SoCs support
  EDAC/i10nm: Add Intel Granite Rapids-D support
  EDAC/mem_repair: Reduce stack usage in edac_mem_repair_get_desc()
  EDAC/igen6: Reduce log level to debug for absent memory controllers
  EDAC/ie31200: Document which CPUs correspond to each Raptor Lake-S device ID
  EDAC/ie31200: Enable support for Core i5-14600 and i7-14700
  ie31200/EDAC: Add Intel Bartlett Lake-S SoCs support
</content>
</entry>
<entry>
<title>EDAC/{skx_common,i10nm}: Use scnprintf() for safer buffer handling</title>
<updated>2025-07-15T17:06:58+00:00</updated>
<author>
<name>Wang Haoran</name>
<email>haoranwangsec@gmail.com</email>
</author>
<published>2025-07-15T13:17:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=35928bc38db69a2af26624e35a250c1e0f9a6a3f'/>
<id>urn:sha1:35928bc38db69a2af26624e35a250c1e0f9a6a3f</id>
<content type='text'>
snprintf() is fragile when its return value will be used to append
additional data to a buffer. Use scnprintf() instead.

Signed-off-by: Wang Haoran &lt;haoranwangsec@gmail.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Tested-by: Qiuxu Zhuo &lt;qiuxu.zhuo@intel.com&gt;
Reviewed-by: Qiuxu Zhuo &lt;qiuxu.zhuo@intel.com&gt;
Link: https://lore.kernel.org/r/20250715131700.1092720-1-haoranwangsec@gmail.com
</content>
</entry>
<entry>
<title>EDAC/synopsys: Clear the ECC counters on init</title>
<updated>2025-07-14T10:15:37+00:00</updated>
<author>
<name>Shubhrajyoti Datta</name>
<email>shubhrajyoti.datta@amd.com</email>
</author>
<published>2025-07-13T05:07:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=b1dc7f097b78eb8d25b071ead2384b07a549692b'/>
<id>urn:sha1:b1dc7f097b78eb8d25b071ead2384b07a549692b</id>
<content type='text'>
Clear the ECC error and counter registers during initialization/probe to avoid
reporting stale errors that may have occurred before EDAC registration.

For that, unify the Zynq and ZynqMP ECC state reading paths and simplify the
code.

  [ bp: Massage commit message.
    Fix an -Wsometimes-uninitialized warning as reported by
    Reported-by: kernel test robot &lt;lkp@intel.com&gt;
    Closes: https://lore.kernel.org/oe-kbuild-all/202507141048.obUv3ZUm-lkp@intel.com ]

Signed-off-by: Shubhrajyoti Datta &lt;shubhrajyoti.datta@amd.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Link: https://lore.kernel.org/20250713050753.7042-1-shubhrajyoti.datta@amd.com
</content>
</entry>
</feed>
