<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/drivers/gpu/host1x/hw, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
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<updated>2026-07-16T18:31:33+00:00</updated>
<entry>
<title>gpu: host1x: Add Tegra264 support</title>
<updated>2026-07-16T18:31:33+00:00</updated>
<author>
<name>Santosh BS</name>
<email>santoshb@nvidia.com</email>
</author>
<published>2026-06-22T06:57:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=60bca008dd78907eff49e38f3c40884c31bc83fb'/>
<id>urn:sha1:60bca008dd78907eff49e38f3c40884c31bc83fb</id>
<content type='text'>
Add device data and chip headers for Tegra264.

Signed-off-by: Santosh BS &lt;santoshb@nvidia.com&gt;
Co-developed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patch.msgid.link/20260622-t264-host1x-v2-4-ff7364d9ff7b@nvidia.com
</content>
</entry>
<entry>
<title>gpu: host1x: Annotate intentional syncpoint wrap-around</title>
<updated>2026-07-16T18:29:47+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2026-06-09T08:09:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=5d4f4018274069d6dd9ec760a29eceb88fc6bd49'/>
<id>urn:sha1:5d4f4018274069d6dd9ec760a29eceb88fc6bd49</id>
<content type='text'>
Host1x syncpoints are 32-bit counters that roll over by design.
To make that explicit in the code, use wrapping_* functions whenever
arithmetic is done on syncpoint values.

Atomic operations cannot be updated but a comment is added.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patch.msgid.link/20260609-b4-host1x-small-fixes-a-v1-6-7c1131c0b3ad@nvidia.com
</content>
</entry>
<entry>
<title>gpu: host1x: Fix offset calculation in trace_write_gather</title>
<updated>2026-07-16T18:29:11+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2026-06-09T08:09:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=eb896850964d3dfce291b4fdff9c2d42d85e564b'/>
<id>urn:sha1:eb896850964d3dfce291b4fdff9c2d42d85e564b</id>
<content type='text'>
When a gather longer than 2*TRACE_MAX_LENGTH (256) words is traced
through host1x_cdma_push_gather, the reported BO offset drifts from
the third iteration onward.

Fix the calculation by properly calculating the value on each loop
rather than accumulating.

In reality, gathers tend to be pretty short so this is unlikely to
ever have been observed.

Fixes: b40d02bf96e0 ("gpu: host1x: Use struct host1x_bo pointers in traces")
Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patch.msgid.link/20260609-b4-host1x-small-fixes-a-v1-3-7c1131c0b3ad@nvidia.com
</content>
</entry>
<entry>
<title>gpu: host1x: Wait for timeout worker completion on channel free</title>
<updated>2026-07-16T18:28:50+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2026-06-09T08:09:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=7a39b9856acccc8e9b05845ca2bf62494fcd3dfa'/>
<id>urn:sha1:7a39b9856acccc8e9b05845ca2bf62494fcd3dfa</id>
<content type='text'>
cdma_timeout_destroy() used cancel_delayed_work() to cancel pending
timeout work when destroying the CDMA. Usually this is fine, but
there is a narrow race condition where the timeout handler has started
execution but has not taken cdma-&gt;lock; the channel is freed causing
cdma_stop to take cdma-&gt;lock and flush the channel; host1x_cdma_deinit
then proceeds with deinitializing cdma while the handler is waiting to
take cdma-&gt;lock.

Therefore change cdma_timeout_destroy to use cancel_delayed_work_sync
instead to ensure any pending timeout work completes before proceeding.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patch.msgid.link/20260609-b4-host1x-small-fixes-a-v1-1-7c1131c0b3ad@nvidia.com
</content>
</entry>
<entry>
<title>gpu: host1x: Syncpoint interrupt performance optimization</title>
<updated>2025-11-14T17:27:19+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2025-09-17T01:48:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=bfe68975768a983d4e59c7fb465301999b863a7e'/>
<id>urn:sha1:bfe68975768a983d4e59c7fb465301999b863a7e</id>
<content type='text'>
Optimize performance of syncpoint interrupt handling by reading
the status register in 64-bit chunks when possible, and skipping
processing when the read value is zero.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patch.msgid.link/20250917-host1x-syncpt-irq-perf-v2-1-736ef69b1347@nvidia.com
</content>
</entry>
<entry>
<title>gpu: host1x: Wait prefences outside MLOCK</title>
<updated>2025-09-11T16:56:35+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2025-07-08T11:25:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=63d47cc6eeb27fa0f5b2d9e2e9b950d728b6ca24'/>
<id>urn:sha1:63d47cc6eeb27fa0f5b2d9e2e9b950d728b6ca24</id>
<content type='text'>
The current submission opcode sequence first takes the engine MLOCK,
and then switches to HOST1X class to wait prefences. This is fine
while we only use a single channel per engine and there is no
virtualization, since jobs are serialized on that one channel anyway.
However, when that assumption doesn't hold, we are keeping the
engine locked while not running anything on it while waiting for
prefences to complete.

To resolve this, execute wait commands in the beginning of the job
outside the engine MLOCK. We still take the HOST1X MLOCK because
recent hardware requires register opcodes to be executed within some
MLOCK, but the hardware also allows unlimited channels to take the
HOST1X MLOCK at the same time.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20250708-host1x-wait-prefences-outside-mlock-v1-1-13e98044e35a@nvidia.com
</content>
</entry>
<entry>
<title>gpu: host1x: Add MLOCK recovery for rest of engines</title>
<updated>2024-08-29T18:14:29+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2024-04-25T05:02:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=57d298bdb46bc240498675a7f887fc71089da2c0'/>
<id>urn:sha1:57d298bdb46bc240498675a7f887fc71089da2c0</id>
<content type='text'>
Add class IDs / MLOCKs for MLOCK recovery for rest of engines
present on Tegra234.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240425050238.2943404-4-cyndis@kapsi.fi
</content>
</entry>
<entry>
<title>gpu: host1x: Handle CDMA wraparound when debug printing</title>
<updated>2024-08-29T18:14:29+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2024-04-25T05:02:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e436a40830f0fda1a1e5e51d3102644f3e0645fa'/>
<id>urn:sha1:e436a40830f0fda1a1e5e51d3102644f3e0645fa</id>
<content type='text'>
During channel debug information dump, when printing CDMA
opcodes, the circular nature of the CDMA pushbuffer wasn't being
taken into account, sometimes accessing past the end. Change
the printing to take this into account.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240425050238.2943404-2-cyndis@kapsi.fi
</content>
</entry>
<entry>
<title>gpu: host1x: Request syncpoint IRQs only during probe</title>
<updated>2024-08-28T15:28:48+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2024-05-31T07:07:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=4c27ac45e6224ea0ca2d2e5dce64e3df122d27c7'/>
<id>urn:sha1:4c27ac45e6224ea0ca2d2e5dce64e3df122d27c7</id>
<content type='text'>
Syncpoint IRQs are currently requested in a code path that runs
during resume. Due to this, we get multiple overlapping registered
interrupt handlers as host1x is suspended and resumed.

Rearrange interrupt code to only request IRQs during initialization.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240531070719.2138-1-cyndis@kapsi.fi
</content>
</entry>
<entry>
<title>gpu: host1x: Syncpoint interrupt sharding</title>
<updated>2023-10-11T20:52:44+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2023-09-01T11:40:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f017f1e9cb3458a86f586a171e284e2ec46286db'/>
<id>urn:sha1:f017f1e9cb3458a86f586a171e284e2ec46286db</id>
<content type='text'>
Support sharded syncpoint interrupts on Tegra234+. This feature
allows specifying one of eight interrupt lines for each syncpoint
to lower processing latency of syncpoint threshold
interrupts.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230901114008.672433-1-cyndis@kapsi.fi
</content>
</entry>
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