kernel/git/stable/linux.git/drivers/iommu/arm, branch linux-7.2.y

iommu/arm-smmu-v3-iommufd: Require exactly one Stream ID for a vDEVICE

2026-07-14T13:51:57+00:00

arm_vsmmu_vsid_to_sid() maps a guest's vSID to a single physical Stream ID taken from master->streams[0], assuming a device has exactly one stream. A device with several streams gets only its first one mapped, so a guest vSID invalidation cannot reach the others' ATC and IOTLB entries; a device with none makes master->streams a ZERO_SIZE_PTR, read out of bounds. Add an arm_vsmmu_vdevice_init() op to reject the vDEVICE with -EOPNOTSUPP when master->num_streams is not one, rather than mapping it silently. Fixes: d68beb276ba26 ("iommu/arm-smmu-v3: Support IOMMU_HWPT_INVALIDATE using a VIOMMU object") Link: https://patch.msgid.link/r/b15f2b73520f389f3f57881da2f040e7bdc18876.1783311134.git.nicolinc@nvidia.com Reviewed-by: Kevin Tian Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen Signed-off-by: Jason Gunthorpe

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of by the more specific where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich Acked-by: Takashi Sakamoto Acked-by: Bjorn Helgaas Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub)

Merge branches 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'rockchip', 'verisilicon', 'riscv', 'intel/vt-d', 'amd/amd-vi' and 'core' into next

2026-06-12T12:57:23+00:00

iommu/arm-smmu-v3: Allow ATS to be always on

2026-05-28T07:34:42+00:00

When a device's default substream attaches to an identity domain, the SMMU driver currently sets the device's STE between two modes: Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1 Mode 2: Cfg=bypass (EATS is ignored by HW) When there is an active PASID (non-default substream), mode 1 is used. And when there is no PASID support or no active PASID, mode 2 is used. The driver will also downgrade an STE from mode 1 to mode 2, when the last active substream becomes inactive. However, there are PCIe devices that demand ATS to be always on. For these devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2. Change the driver accordingly: - always use the mode 1 - never downgrade to mode 2 - allocate and retain a CD table (see note below) Note that these devices might not support PASID, i.e. doing non-PASID ATS. In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to a !0 value in order to keep the S1DSS field effective. Thus, when a master requires ats_always_on, set its s1cdmax to at least 1, meaning that the CD table will have a dummy entry (SSID=1) that will never be used. Now for these devices, arm_smmu_cdtab_allocated() will always return true, v.s. false prior to this change. When its default substream is attached to an IDENTITY domain, its first CD is NULL in the table, which is a totally valid case. Thus, add "!master->ats_always_on" to the condition. Reviewed-by: Jonathan Cameron Tested-by: Nirmoy Das Acked-by: Nirmoy Das Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Reviewed-by: Dave Jiang Signed-off-by: Nicolin Chen Signed-off-by: Joerg Roedel

iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits

2026-05-19T14:08:09+00:00

HTTU is introduced by utilizing the Dirty Bit Modifier (DBM) in the PTE. When kernel maps a clean but writable page, it will set PTE_READONLY and PTE_DBM (aka PTE_WRITE) at the same time. When a write occurs, an HTTU- capable MMU will automatically clear the PTE_RDONLY bit without software intervention. On the other hand, SMMU has the same HTTU feature, yet it is not enabled in the SVA CD. As a result, SMMU will not clear the PTE_RDONLY bit while sharing the CPU page table, resulting in unnecessary stalls. Thus, enable CTXDESC_CD_0_TCR_HA and CTXDESC_CD_0_TCR_HD in the SVA CD. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Signed-off-by: Will Deacon

iommu/arm-smmu-v3: Directly encode TLBI commands

2026-05-19T14:06:12+00:00

TLBI is more complicated than all the other commands because the invalidation loop builds a template command from the struct arm_smmu_inv which is then expanded into many TLBI commands for the invalidation. Reviewed-by: Mostafa Saleh Reviewed-by: Pranjal Shrivastava Tested-by: Pranjal Shrivastava Tested-by: Mostafa Saleh Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Tested-by: Samiullah Khawaja Tested-by: Nicolin Chen Signed-off-by: Will Deacon

iommu/arm-smmu-v3: Directly encode CMDQ_OP_SYNC

2026-05-19T14:06:12+00:00

Change the flow so the caller controls the CS field and remove the weird u64p_replace_bits() thing to override it. Reviewed-by: Pranjal Shrivastava Reviewed-by: Mostafa Saleh Tested-by: Pranjal Shrivastava Tested-by: Mostafa Saleh Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Tested-by: Samiullah Khawaja Tested-by: Nicolin Chen Signed-off-by: Will Deacon

iommu/arm-smmu-v3: Directly encode CMDQ_OP_ATC_INV

2026-05-19T14:06:12+00:00

Add a new command make function and convert all the places using ATC_INV. Split out full invalidation to directly make the cmd instead of overloading size=0 to mean full invalidation. In section "3.9.1 ATS Interface" of F.b the specification says: When the SMMU returns an ATS Translation Completion for a request that had a PASID, the Global bit of the Translation Completion Data Entry must be zero. Even though it faithfully forwards the G bit through to the ATS invalidation command there is no way to create G mappings so there is never any need to send a G invalidation. Thus don't expose global in the new helpers and leave CMDQ_ATC_0_GLOBAL unused. Reviewed-by: Mostafa Saleh Reviewed-by: Pranjal Shrivastava Tested-by: Pranjal Shrivastava Tested-by: Mostafa Saleh Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Tested-by: Samiullah Khawaja Tested-by: Nicolin Chen Signed-off-by: Will Deacon

iommu/arm-smmu-v3: Directly encode simple commands

2026-05-19T14:06:12+00:00

Add make functions to build commands for CMDQ_OP_TLBI_EL2_ALL CMDQ_OP_TLBI_NSNH_ALL CMDQ_OP_CFGI_ALL CMDQ_OP_PREFETCH_CFG CMDQ_OP_CFGI_STE CMDQ_OP_CFGI_CD CMDQ_OP_RESUME CMDQ_OP_PRI_RESP Convert all of these call sites to use the make function instead of going through arm_smmu_cmdq_build_cmd(). Use a #define so the general pattern is always: arm_smmu_cmdq_issue_cmd(smmu, arm_smmu_make_cmd_XX(..)); Add arm_smmu_cmdq_batch_add_cmd() which takes struct arm_smmu_cmd directly to match the new flow. Reviewed-by: Pranjal Shrivastava Reviewed-by: Mostafa Saleh Tested-by: Pranjal Shrivastava Tested-by: Mostafa Saleh Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Tested-by: Samiullah Khawaja Tested-by: Nicolin Chen Signed-off-by: Will Deacon

iommu/arm-smmu-v3: Remove CMDQ_OP_CFGI_CD_ALL from arm_smmu_cmdq_build_cmd()

2026-05-19T14:06:12+00:00

Nothing uses this, just dead code. Reviewed-by: Mostafa Saleh Reviewed-by: Pranjal Shrivastava Tested-by: Pranjal Shrivastava Tested-by: Mostafa Saleh Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Tested-by: Samiullah Khawaja Tested-by: Nicolin Chen Signed-off-by: Will Deacon