<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/drivers/net/e1000e/hw.h, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master'/>
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<updated>2011-08-11T03:03:27+00:00</updated>
<entry>
<title>intel: Move the Intel wired LAN drivers</title>
<updated>2011-08-11T03:03:27+00:00</updated>
<author>
<name>Jeff Kirsher</name>
<email>jeffrey.t.kirsher@intel.com</email>
</author>
<published>2011-04-07T14:42:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=dee1ad47f2ee75f5146d83ca757c1b7861c34c3b'/>
<id>urn:sha1:dee1ad47f2ee75f5146d83ca757c1b7861c34c3b</id>
<content type='text'>
Moves the Intel wired LAN drivers into drivers/net/ethernet/intel/ and
the necessary Kconfig and Makefile changes.

Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: access multiple PHY registers on same page at the same time</title>
<updated>2011-06-10T03:33:36+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-05-13T07:20:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=2b6b168d52aa044363647cfff8bda5cef8068ca3'/>
<id>urn:sha1:2b6b168d52aa044363647cfff8bda5cef8068ca3</id>
<content type='text'>
Doing a PHY page select can take a long time, relatively speaking. This
can cause a significant delay when updating a number of PHY registers on
the same page by unnecessarily setting the page for each PHY access. For
example when going to Sx, all the PHY wakeup registers (WUC, RAR[], MTA[],
SHRAR[], IP4AT[], IP6AT[], etc.) on 82577/8/9 need to be updated which
takes a long time which can cause issues when suspending.

This patch introduces new PHY ops function pointers to allow callers to
set the page directly and do any number of PHY accesses on that page.
This feature is currently only implemented for 82577, 82578 and 82579
PHYs for both the normally addressed registers as well as the special-
case addressing of the PHY wakeup registers on page 800. For the latter
registers, the existing function for accessing the wakeup registers has
been divided up into three- 1) enable access to the wakeup register page,
2) perform the register access and 3) disable access to the wakeup register
page. The two functions that enable/disable access to the wakeup register
page are necessarily available to the caller so that the caller can restore
the value of the Port Control (a.k.a. Wakeup Enable) register after the
wakeup register accesses are done.

All instances of writing to multiple PHY registers on the same page are
updated to use this new method and to acquire any PHY locking mechanism
before setting the page and performing the register accesses, and release
the locking mechanism afterward.

Some affiliated magic number cleanup is done as well.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: disable far-end loopback mode on ESB2</title>
<updated>2011-06-10T03:31:24+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-05-13T07:19:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d9b24135b972ccdd5f5174fba06c730e895e6daf'/>
<id>urn:sha1:d9b24135b972ccdd5f5174fba06c730e895e6daf</id>
<content type='text'>
The ESB2 LAN includes a debug feature that enables far-end loopback (FELB)
of the SerDes/Kumeran interface.  This feature is activated when receiving
a sequence of symbols that includes a reserved codeword.  On a perfect
link, FELB would never be activated.  In the presence of bit errors, there
is a very small, but non-zero, probability of FELB being activated.

If the FELB is activated, the SerDes link becomes non-functional and must
be reset.  It could also corrupt the switching tables in the switch since
the ESB2 is transmitting packets with a different source MAC address.

This patch disables the FELB feature.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: implement ethtool set_phys_id</title>
<updated>2011-04-27T09:05:53+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-04-16T00:34:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=dbf80dcbd8ca0c50f343401fedd2d6200cb8097e'/>
<id>urn:sha1:dbf80dcbd8ca0c50f343401fedd2d6200cb8097e</id>
<content type='text'>
Based on a patch from Stephen Hemminger &lt;shemminger@vyatta.com&gt;.

The new ethtool set_phys_id takes over controlling the LED for
identifying boards.  This fixes the lockout during that period.
For this device lots of extra infrastructure can also be removed by
using set_phys_id.

v2: - return blink frequency for parts that do not support blink in h/w
    - add blink_led function pointers for devices that do support blink
      in h/w to cleanup the test for this functionality

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Cc: Stephen Hemminger &lt;shemminger@vyatta.com&gt;
Tested-by: Aaron Brown &lt;aaron.f.brown@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: magic number cleanup - ETH_ALEN</title>
<updated>2011-03-11T09:52:40+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-02-25T07:09:37+00:00</published>
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<id>urn:sha1:d8d5f8aebb857f979fbe9099c9acc2ed486706be</id>
<content type='text'>
Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: consistent use of Rx/Tx vs. RX/TX/rx/tx in comments/logs</title>
<updated>2011-01-14T10:06:23+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2010-12-31T06:10:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=af667a29dd3dfc0464f83bac30cc3c63fe5d0206'/>
<id>urn:sha1:af667a29dd3dfc0464f83bac30cc3c63fe5d0206</id>
<content type='text'>
Some minor comment errors and whitespace issues discovered while looking
into this are also addressed.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: update Copyright for 2011</title>
<updated>2011-01-14T10:04:01+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-01-04T01:16:44+00:00</published>
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<id>urn:sha1:0d6057e48b9d2004024e97252da83dce0661b131</id>
<content type='text'>
Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>e1000e: add custom set_d[0|3]_lplu_state function pointer for 82574</title>
<updated>2011-01-10T07:44:09+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2011-01-06T14:29:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=77996d1d4c1cf0059f5c2d1cea9d5135ac1b8c91'/>
<id>urn:sha1:77996d1d4c1cf0059f5c2d1cea9d5135ac1b8c91</id>
<content type='text'>
82574 needs to configure Low Power Link Up (or LPLU) differently than
the other parts in the 8257x family supported by the driver.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Emil Tantilov &lt;emil.s.tantilov@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>e1000e: 82579 unaccounted missed packets</title>
<updated>2010-09-23T03:41:20+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2010-09-22T17:16:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=831bd2e6a6c09588fdde453ecb858f050ac1b942'/>
<id>urn:sha1:831bd2e6a6c09588fdde453ecb858f050ac1b942</id>
<content type='text'>
On 82579, there is a hardware bug that can cause received packets to not
get transferred from the PHY to the MAC due to K1 (a power saving feature
of the PHY-MAC interconnect similar to ASPM L1).  Since the MAC controls
the accounting of missed packets, these will go unnoticed.  Workaround the
issue by setting the K1 beacon duration according to the link speed.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>e1000e: correct MAC-PHY interconnect register offset for 82579</title>
<updated>2010-08-03T23:40:53+00:00</updated>
<author>
<name>Bruce Allan</name>
<email>bruce.w.allan@intel.com</email>
</author>
<published>2010-08-03T11:48:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=96f2bd13bfb6df5beec7fe55405ad94b528b8b4c'/>
<id>urn:sha1:96f2bd13bfb6df5beec7fe55405ad94b528b8b4c</id>
<content type='text'>
The MAC-PHY interconnect register set on ICH/PCH parts is accessed through
a peephole mechanism by writing an offset to a CSR register.  The offset
for the interconnect's half-duplex control register (which is used in a
jumbo frame workaround for 82579) is incorrect.

Signed-off-by: Bruce Allan &lt;bruce.w.allan@intel.com&gt;
Tested-by: Jeff Pieper &lt;jeffrey.e.pieper@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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