kernel/git/stable/linux.git/drivers/phy/freescale, branch linux-6.10.y

phy: fsl-imx8mq-usb: fix tuning parameter name

2024-09-04T11:30:06+00:00

commit ce52c2532299c7ccfd34a52db8d071e890a78c59 upstream. According to fsl,imx8mq-usb-phy.yaml, this tuning parameter should be fsl,phy-pcs-tx-deemph-3p5db-attenuation-db. Fixes: 63c85ad0cd81 ("phy: fsl-imx8mp-usb: add support for phy tuning") Cc: stable@vger.kernel.org Signed-off-by: Xu Yang Reviewed-by: Alexander Stein Link: https://lore.kernel.org/r/20240801124642.1152838-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman

phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void

2024-04-12T09:48:42+00:00

The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20240409161505.66619-2-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul

Merge branch 'fixes' into next

2024-04-12T09:31:28+00:00

This brings rockchip,pcie3-phy changes into next which incoming patches are dependent on

phy: freescale: imx8m-pcie: fix pcie link-up instability

2024-04-06T07:13:16+00:00

Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock) proves to be more stable on the i.MX 8M Mini. Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by: Marcel Ziswiler Reviewed-by: Richard Zhu Link: https://lore.kernel.org/r/20240322130646.1016630-2-marcel@ziswiler.com Signed-off-by: Vinod Koul

phy: freescale: add Samsung HDMI PHY

2024-03-28T18:57:06+00:00

This adds the driver for the Samsung HDMI PHY found on the i.MX8MP SoC. Based on downstream implementation from Sandor Yu . According to the TRM, the PHY receives parallel data from the link and serializes it. It also sets the PLL clock needed for the TX serializer. Tested-by: Luca Ceresoli Tested-by: Richard Leitner Co-developed-by: Marco Felsch Signed-off-by: Marco Felsch Signed-off-by: Lucas Stach Tested-by: Alexander Stein Tested-by: Frieder Schrempf # Kontron BL Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli Tested-by: Tommaso Merciai Link: https://lore.kernel.org/r/20240227220444.77566-3-aford173@gmail.com Signed-off-by: Vinod Koul

Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2024-03-16T18:24:51+00:00

Pull phy updates from Vinod Koul: "New hardware support: - Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS PHY and SDM630 USBC support - Rockchip HDMI/eDP Combo PHY driver - Mediatek MT8365 CSI phy driver Updates: - Rework on Qualcomm phy PCS registers and type-c handling - Cadence torrent phy updates for multilink configuration - TI gmii resume support" * tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits) phy: constify of_phandle_args in xlate phy: ti: tusb1210: Define device IDs phy: ti: tusb1210: Use temporary variable for struct device phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema phy: ti: gmii-sel: add resume support phy: mtk-mipi-csi: add driver for CSI phy dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200 dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200 phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1 phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API dt-bindings: phy: qmp-ufs: Fix PHY clocks phy: qcom: sgmii-eth: move PCS registers to separate header phy: qcom: sgmii-eth: use existing register definitions phy: qcom: qmp-usbc: drop has_pwrdn_delay handling phy: qcom: qmp: move common bits definitions to common header phy: qcom: qmp: split DP PHY registers to separate headers ...

phy: constify of_phandle_args in xlate

2024-02-23T12:13:14+00:00

The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski Acked-by: Thierry Reding Acked-by: Linus Walleij Acked-by: Florian Fainelli #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul

phy: freescale: phy-fsl-imx8-mipi-dphy: Fix alias name to use dashes

2024-02-07T10:19:40+00:00

Devicetree spec lists only dashes as valid characters for alias names. Table 3.2: Valid characters for alias names, Devicee Specification, Release v0.4 Signed-off-by: Alexander Stein Fixes: 3fbae284887de ("phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support") Link: https://lore.kernel.org/r/20240110093343.468810-1-alexander.stein@ew.tq-group.com Signed-off-by: Vinod Koul

phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registers

2023-10-06T09:59:52+00:00

The protocol converter configuration registers PCC8, PCCC, PCCD (implemented by the driver), as well as others, control protocol converters from multiple lanes (each represented as a different struct phy). So, if there are simultaneous calls to phy_set_mode_ext() to lanes sharing the same PCC register (either for the "old" or for the "new" protocol), corruption of the values programmed to hardware is possible, because lynx_28g_rmw() has no locking. Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take the global spinlock from the phy_ops :: set_mode() implementation. There are no other callers which modify PCC registers. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller

phy: lynx-28g: lock PHY while performing CDR lock workaround

2023-10-06T09:59:52+00:00

lynx_28g_cdr_lock_check() runs once per second in a workqueue to reset the lane receiver if the CDR has not locked onto bit transitions in the RX stream. But the PHY consumer may do stuff with the PHY simultaneously, and that isn't okay. Block concurrent generic PHY calls by holding the PHY mutex from this workqueue. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller