kernel/git/stable/linux.git/drivers/pinctrl/aspeed, branch master

Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2026-08-24T15:46:03+00:00

Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of by the more specific where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich Acked-by: Takashi Sakamoto Acked-by: Bjorn Helgaas Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub)

pinctrl: aspeed: Split TRST out of the AST2700 SoC1 JTAGM1 group

2026-06-30T11:52:19+00:00

The JTAGM1 group includes the D12 ball carrying the TRST signal, but TRST is optional for a JTAG master and the ball may be needed for other functions on designs that do not wire it. With TRST embedded in the group, such designs cannot use the JTAG master at all. Move D12 into a new JTAGM1TRST group under the same JTAGM1 function so TRST is muxed only when a board requests it. Boards that do use TRST now need to select both the JTAGM1 and JTAGM1TRST groups. Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij

pinctrl: aspeed: Fix GPIO mux value for ADC-capable balls

2026-06-08T08:18:52+00:00

aspeed_g7_soc1_gpio_request_enable() unconditionally writes mux function 0 to route the requested pin to GPIO. This is wrong for the ADC-capable balls W17 through AB19 (ADC0-ADC15), where function 0 selects the ADC input and function 1 selects GPIO. Requesting one of those GPIOs therefore muxed the ball to ADC instead. Write mux value 1 for balls W17 through AB19 so the GPIO function is actually selected. Fixes: 4af4eb66aac3 ("pinctrl: aspeed: Add AST2700 SoC1 support") Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij

pinctrl: aspeed: Add AST2700 SoC1 support

2026-05-25T08:04:32+00:00

Implement pin multiplexing (and pin configuration where applicable) for the AST2700 SoC1 SCU pinctrl block using static SoC data tables. Unlike legacy ASPEED pin controllers, the SoC1 pin function control fields are highly regular, which makes it practical to describe the packed-field register layout directly in driver data rather than reuse the existing Aspeed pinctrl macro infrastructure. The driver uses the generic pinctrl, pinmux and pinconf frameworks. The controller registers are accessed via regmap from the parent syscon, allowing shared ownership of the SCU register block. Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij

pinctrl: aspeed: Add AST2700 SoC0 support

2026-05-11T20:03:24+00:00

Add pinctrl support for the SoC0 instance of the ASPEED AST2700. AST2700 consists of two interconnected SoC instances, each with its own pinctrl register block. The SoC0 pinctrl hardware closely follows the design found in previous ASPEED BMC generations, allowing the driver to build upon the common ASPEED pinctrl infrastructure. Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij

pinctrl: aspeed: Cleanup header includes

2026-01-19T00:11:46+00:00

Remove unused includes (no mutexes, string functions, no OF functions) and bring directly used mod_devicetable.h (previously pulled via of.h). Reviewed-by: Andrew Jeffery Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij

pinctrl: aspeed: g5: Constrain LPC binding revision workaround to AST2500

2026-01-09T13:33:37+00:00

Discovering a phandle to an AST2400 or AST2600 LPC node indicates an error for the purpose of the AST2500 pinctrl driver. Signed-off-by: Andrew Jeffery Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij

pinctrl: aspeed-g6: Add PCIe RC PERST pin group

2025-07-23T11:22:41+00:00

The PCIe RC PERST uses SSPRST# as PERST# and enable this pin to output. Signed-off-by: Jacky Chou Acked-by: Linus Walleij Link: https://lore.kernel.org/20250715034320.2553837-8-jacky_chou@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: aspeed: Constify static 'pinctrl_desc'

2025-06-18T11:26:36+00:00

The local static 'struct pinctrl_desc' is not modified, so can be made const for code safety. Reviewed-by: Andrew Jeffery Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20250611-pinctrl-const-desc-v2-5-b11c1d650384@linaro.org Signed-off-by: Linus Walleij