<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/drivers/pinctrl/qcom, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/'/>
<updated>2026-08-24T15:46:03+00:00</updated>
<entry>
<title>Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2026-08-24T15:46:03+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-08-24T15:46:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=cf9610f9116d55c5a66ef9f1faecacabd93a9322'/>
<id>urn:sha1:cf9610f9116d55c5a66ef9f1faecacabd93a9322</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "Core changes:

   - Use the non-blocking mux_state_try_select() in the generic MUX pin
     control back-end

   - Free pin maps on pinctrl_generic_to_map() failure in the core
     helpers

  New hardware pin control:

   - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC
     (this is for the low power audio, LPASS = Low Power Audio SubSystem
     portions)

   - Upboard support on top of the Intel pin controller

   - Apple T6030 and T6031 support (just compatible strings)

   - Samsung Exynos 8855 SoC

   - Mediatek MT6858 SoC

   - Rockchip RK3308B and RV1106 SoCs

   - Airoha EN7523 and AN7563 SoCs

  Improvements:

   - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable

   - Qualcomm improvements on top of the Qualcomm PDC (power domain
     controller) irqchip improvements from tglx:s tree

   - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups

   - The NPCM8xx driver has been put into shape fixing many pin and
     group definitions

   - Some non-urgent Tegra 264 pin assignments are fixed up

   - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and
     pin assignments, missing features etc"

* tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits)
  dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema
  pinctrl: meson: sync some modify from A4
  pinctrl: meson: a4: Add input enable pin configuration
  pinctrl: realtek: rtd1625: remove unused group name spdif_sel
  pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13
  dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema
  Revert "Merge branch 'ib-rsk7204' into devel"
  pinctrl: rockchip: Add RV1106 pinctrl support
  dt-bindings: pinctrl: rockchip: Add RV1106 compatible
  pinctrl: rockchip: Decode drive strength in the get function
  pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable
  pinctrl: airoha: add support of an7563 SoC
  dt-bindings: pinctrl: airoha: add support of an7563 pin controller
  pinctrl: airoha: try to find chip scu node by phandle first
  pinctrl: airoha: add support of en7523 SoC
  dt-bindings: pinctrl: airoha: add support of en7523 pin controller
  pinctrl: airoha: an7583: add support for olt pinmux
  pinctrl: airoha: an7583: add support for pon_alt pinmux
  pinctrl: airoha: an7583: add support for npu_uart pinmux
  dt-bindings: pinctrl: airoha: an7583: add missed features
  ...
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-qcom-updates-for-v7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel</title>
<updated>2026-08-16T16:59:43+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linusw@kernel.org</email>
</author>
<published>2026-08-16T16:59:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d067f0f4c96cb5402a111cf649b7bf9c5771ec74'/>
<id>urn:sha1:d067f0f4c96cb5402a111cf649b7bf9c5771ec74</id>
<content type='text'>
Qualcomm pinctrl updates for v7.3-rc1

New drivers:
- add pinctrl drivers for Maili TLMM and Elize LPASS LPI TLMM controllers

Driver updates:
- acknowledge interrupts for the PDC interrupt controller in pinctrl-msm
- implement irq_get/set_irqchip_state() for pinctrl-msm
- add support for a new model to Qualcomm pinctrl-spmi-gpio
- drop some dead code from qcom pinctrl modules

Devicetree bindings:
- document new TLMM controllers and the new model for the SPMI GPIO

Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-qcom-fixes-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel</title>
<updated>2026-08-16T16:59:23+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linusw@kernel.org</email>
</author>
<published>2026-08-16T16:59:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e4c90e39c941b1ecf52f01dc35a119293d1bd8ab'/>
<id>urn:sha1:e4c90e39c941b1ecf52f01dc35a119293d1bd8ab</id>
<content type='text'>
Qualcomm pin control fixes for v7.2

- fix intr_target_width for summary interrupt routing in pinctrl-shikra

Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Use IRQ trigger mask helpers</title>
<updated>2026-08-06T21:40:54+00:00</updated>
<author>
<name>Maulik Shah</name>
<email>maulik.shah@oss.qualcomm.com</email>
</author>
<published>2026-08-02T14:05:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=aef612f013de95bfe01b9b4c3a3231c4327cd3ab'/>
<id>urn:sha1:aef612f013de95bfe01b9b4c3a3231c4327cd3ab</id>
<content type='text'>
Use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH instead of open-coded
trigger type combinations in irqchip callbacks.

No functional change intended.

Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Maulik Shah &lt;maulik.shah@oss.qualcomm.com&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-qcom-fixes-for-v7.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into fixes</title>
<updated>2026-08-03T07:54:28+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linusw@kernel.org</email>
</author>
<published>2026-08-03T07:54:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=696ff859f5f93a7cedab2a2afa20bd1635918fcf'/>
<id>urn:sha1:696ff859f5f93a7cedab2a2afa20bd1635918fcf</id>
<content type='text'>
Qualcomm pin control fixes for v7.2-rc6

- mark gpio and pci reset as a GPIO pin functions in pinctrl-ipq8064
- fix audio_sec_mclk_in1/out1 pin numbers in pinctrl-ipq9650

Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: shikra: Fix intr_target_width for summary interrupt routing</title>
<updated>2026-07-31T08:31:21+00:00</updated>
<author>
<name>Komal Bajaj</name>
<email>komal.bajaj@oss.qualcomm.com</email>
</author>
<published>2026-07-28T11:03:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=1e7b04c12c077e8829991833a9aa2cb3bdacab61'/>
<id>urn:sha1:1e7b04c12c077e8829991833a9aa2cb3bdacab61</id>
<content type='text'>
The intr_target_width field sets the mask width used when writing
target processor into interrupt config register and deciding which
processor receives summary interrupt for a given GPIO.

Without it, pinctrl driver defaults to a 3-bit mask. On Shikra, this
field is 4 bits wide, which could corrupt adjacent bits and mis-route
interrupts. Set intr_target_width = 4 to match the hardware.

Fixes: 9db68ec534c5 ("pinctrl: qcom: Add Shikra pinctrl driver")
Signed-off-by: Komal Bajaj &lt;komal.bajaj@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260728-shikra-pinctrl-intr-width-v1-1-46583734d808@oss.qualcomm.com
Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@oss.qualcomm.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: ipq806x: mark pci reset as a GPIO pin function</title>
<updated>2026-07-28T09:11:20+00:00</updated>
<author>
<name>Hans Ulli Kroll</name>
<email>linux@ulli-kroll.de</email>
</author>
<published>2026-07-19T13:36:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=fd46760956509f580f7d3d25db4de10e7c6f949b'/>
<id>urn:sha1:fd46760956509f580f7d3d25db4de10e7c6f949b</id>
<content type='text'>
The qcom pinctrl core supports marking functions that represent GPIO mode
via PINCTRL_GPIO_PINFUNCTION(), so that strict pinmuxing does not reject
GPIO requests for pins that are muxed to the GPIO function.

Mark PCIe reset as GPIO pin function

This allows ipq806x to keep the PCIe-reset related configuration in DTS
without tripping over strict pinmux ownership checks.

Fixes: cc85cb96e2e4 ("pinctrl: qcom: make the pinmuxing strict")
Signed-off-by: Hans Ulli Kroll &lt;linux@ulli-kroll.de&gt;
Acked-by: Linus Walleij &lt;linusw@kernel.org&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260719134548.8830-3-linux@ulli-kroll.de
Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@oss.qualcomm.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: ipq806x: mark gpio as a GPIO pin function</title>
<updated>2026-07-28T09:11:20+00:00</updated>
<author>
<name>Hans Ulli Kroll</name>
<email>linux@ulli-kroll.de</email>
</author>
<published>2026-07-19T13:35:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=687f39faccba29ab26de965411db37e849af8ec2'/>
<id>urn:sha1:687f39faccba29ab26de965411db37e849af8ec2</id>
<content type='text'>
The qcom pinctrl core supports marking functions that represent GPIO mode
via PINCTRL_GPIO_PINFUNCTION(), so that strict pinmuxing does not reject
GPIO requests for pins that are muxed to the GPIO function.

Add a IPQ_GPIO_PIN_FUNCTION() helper and use it for the ipq806x gpio
function, matching how the msm-based qcom drivers handle this.

This allows ipq806x to keep the GPIO-related configuration in DTS
without tripping over strict pinmux ownership
checks.

Fixes: cc85cb96e2e4 ("pinctrl: qcom: make the pinmuxing strict")
Signed-off-by: Hans Ulli Kroll &lt;linux@ulli-kroll.de&gt;
Acked-by: Linus Walleij &lt;linusw@kernel.org&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260719134548.8830-2-linux@ulli-kroll.de
Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@oss.qualcomm.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v7.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2026-07-27T15:48:48+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-07-27T15:48:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e63c75f72faa04af24e4b11d4047e7ac1e80ba5b'/>
<id>urn:sha1:e63c75f72faa04af24e4b11d4047e7ac1e80ba5b</id>
<content type='text'>
Pull pin control fixes from Linus Walleij:
 "The most interesting commit is the S4 fix for AMD, which probably is
  helpful to a whole bunch of important machines.

   - Wakeup nits on the Qualcomm SC8280XP

   - Double-free issues on the device tree parsing error path

   - Fixup of the S4 sleep state handling on AMD pin control

   - Missing Kconfig select REGMAP_MMIO for the Microchip driver leading
     to compile stalls

   - Missing Kconfig select GENERIC_PINCONF for the Bitmain BM1880
     leading to compile stalls"

* tag 'pinctrl-v7.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: bm1880: add missing select GENERIC_PINCONF
  pinctrl-amd: Don't clear S4 wake bits at probe
  pinctrl: microchip-sgpio: add missing select REGMAP_MMIO
  pinctrl: devicetree: don't free uninitialized dev_name on error path
  pinctrl: qcom: sc8280xp: Add missing wakeup entries for GPIO143/151
  pinctrl: qcom: Unconditionally mark gpio as wakeup enable
</content>
</entry>
<entry>
<title>pinctrl: qcom: ipq9650: fix audio_sec_mclk_in1/out1 group pins</title>
<updated>2026-07-27T14:48:20+00:00</updated>
<author>
<name>Taceddin Sancak</name>
<email>ts.solidarity@gmail.com</email>
</author>
<published>2026-07-18T00:21:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=4a2e2c563b0ee2253a7902f775bf71232820186d'/>
<id>urn:sha1:4a2e2c563b0ee2253a7902f775bf71232820186d</id>
<content type='text'>
The audio_sec_mclk_in1 and audio_sec_mclk_out1 groups both list
"gpio37", but in the pingroup table those functions are muxed on
gpio39, while gpio37 provides the audio_sec_mclk_in0/out0 variants.
This makes both functions unusable: selecting them on gpio39 is
rejected by the pinmux core because the group is not listed for the
function, and selecting them on gpio37 trips the WARN_ON() in
msm_pinmux_set_mux() and fails with -EINVAL because that group
cannot mux them.

Point both groups at gpio39, matching the pingroup table. This also
mirrors the primary audio MCLK pair, where the mclk0 and mclk1
variants live on separate pins (gpio53 and gpio51 respectively).

Fixes: 3c8e7ba0e399 ("pinctrl: qcom: Introduce IPQ9650 TLMM driver")
Assisted-by: Claude:claude-fable-5
Signed-off-by: Taceddin Sancak &lt;ts.solidarity@gmail.com&gt;
Acked-by: Linus Walleij &lt;linusw@kernel.org&gt;
Reviewed-by: Kathiravan Thirumoorthy &lt;kathiravan.thirumoorthy@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260718002146.698973-1-ts.solidarity@gmail.com
Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@oss.qualcomm.com&gt;
</content>
</entry>
</feed>
