kernel/git/stable/linux.git/drivers/scsi/ufs/Makefile, branch master

scsi: ufs: Split the drivers/scsi/ufs directory

2022-05-20T00:27:37+00:00

Split the drivers/scsi/ufs directory into 'core' and 'host' directories under the drivers/ufs/ directory. Move shared header files into the include/ufs/ directory. This separation makes it clear which header files UFS drivers are allowed to include (include/ufs/*.h) and which header files UFS drivers are not allowed to include (drivers/ufs/core/*.h). Update the MAINTAINERS file. Add myself as a UFS reviewer. Link: https://lore.kernel.org/r/20220511212552.655341-1-bvanassche@acm.org Cc: Adrian Hunter Cc: Avri Altman Cc: Bean Huo Cc: Bjorn Andersson Cc: Keoseong Park Tested-by: Bean Huo Tested-by: Adrian Hunter Reviewed-by: Bean Huo Acked-by: Avri Altman Acked-by: Adrian Hunter Signed-off-by: Bart Van Assche Signed-off-by: Martin K. Petersen

scsi: ufs: core: Probe for temperature notification support

2021-09-22T04:07:42+00:00

Probe the dExtendedUFSFeaturesSupport register for the device's temperature notification support and, if supported, add a hardware monitor device. Link: https://lore.kernel.org/r/20210915060407.40-2-avri.altman@wdc.com Reviewed-by: Guenter Roeck Reviewed-by: Bean Huo Reviewed-by: Daejun Park Signed-off-by: Avri Altman Signed-off-by: Martin K. Petersen

scsi: ufs: Add fault injection support

2021-08-03T11:27:42+00:00

Make it easier to test the UFS error handler and abort handler. Link: https://lore.kernel.org/r/20210722033439.26550-19-bvanassche@acm.org Acked-by: Bean Huo Signed-off-by: Bart Van Assche Signed-off-by: Martin K. Petersen

scsi: ufs: ufshpb: Introduce Host Performance Buffer feature

2021-08-01T20:04:23+00:00

Implement Host Performance Buffer (HPB) initialization and add function calls to UFS core driver. NAND flash-based storage devices, including UFS, have mechanisms to translate logical addresses of I/O requests to the corresponding physical addresses of the flash storage. In UFS, logical-to-physical-address (L2P) map data, which is required to identify the physical address for the requested I/Os, can only be partially stored in SRAM from NAND flash. Due to this partial loading, accessing the flash address area, where the L2P information for that address is not loaded in the SRAM, can result in serious performance degradation. The basic concept of HPB is to cache L2P mapping entries in host system memory so that both physical block address (PBA) and logical block address (LBA) can be delivered in HPB read command. The HPB read command allows to read data faster than a regular read command in UFS since it provides the physical address (HPB Entry) of the desired logical block in addition to its logical address. The UFS device can access the physical block in NAND directly without searching and uploading L2P mapping table. This improves read performance because the NAND read operation for uploading L2P mapping table is removed. In HPB initialization, the host checks if the UFS device supports HPB feature and retrieves related device capabilities. Then, HPB parameters are configured in the device. Total start-up time of popular applications was measured and the difference observed between HPB being enabled and disabled. Popular applications are 12 game apps and 24 non-game apps. Each test cycle consists of running 36 applications in sequence. We repeated the cycle for observing performance improvement by L2P mapping cache hit in HPB. The following is the test environment: - kernel version: 4.4.0 - RAM: 8GB - UFS 2.1 (64GB) Results: +-------+----------+----------+-------+ | cycle | baseline | with HPB | diff | +-------+----------+----------+-------+ | 1 | 272.4 | 264.9 | -7.5 | | 2 | 250.4 | 248.2 | -2.2 | | 3 | 226.2 | 215.6 | -10.6 | | 4 | 230.6 | 214.8 | -15.8 | | 5 | 232.0 | 218.1 | -13.9 | | 6 | 231.9 | 212.6 | -19.3 | +-------+----------+----------+-------+ We also measured HPB performance using iozone: $ iozone -r 4k -+n -i2 -ecI -t 16 -l 16 -u 16 -s $IO_RANGE/16 -F \ mnt/tmp_1 mnt/tmp_2 mnt/tmp_3 mnt/tmp_4 mnt/tmp_5 mnt/tmp_6 mnt/tmp_7 \ mnt/tmp_8 mnt/tmp_9 mnt/tmp_10 mnt/tmp_11 mnt/tmp_12 mnt/tmp_13 \ mnt/tmp_14 mnt/tmp_15 mnt/tmp_16 Results: +----------+--------+---------+ | IO range | HPB on | HPB off | +----------+--------+---------+ | 1 GB | 294.8 | 300.87 | | 4 GB | 293.51 | 179.35 | | 8 GB | 294.85 | 162.52 | | 16 GB | 293.45 | 156.26 | | 32 GB | 277.4 | 153.25 | +----------+--------+---------+ Link: https://lore.kernel.org/r/20210712085830epcms2p8c1288b7f7a81b044158a18232617b572@epcms2p8 Reported-by: kernel test robot Tested-by: Bean Huo Tested-by: Can Guo Tested-by: Stanley Chu Reviewed-by: Greg Kroah-Hartman Reviewed-by: Bart Van Assche Reviewed-by: Can Guo Reviewed-by: Bean Huo Reviewed-by: Stanley Chu Acked-by: Avri Altman Signed-off-by: Daejun Park Signed-off-by: Martin K. Petersen

scsi: ufs: ufs-debugfs: Add error counters

2021-01-13T03:14:06+00:00

People testing have a need to know how many errors might be occurring over time. Add error counters and expose them via debugfs. A module initcall is used to create a debugfs root directory for ufshcd-related items. In the case that modules are built-in, then initialization is done in link order, so move ufshcd-core to the top of the Makefile. Link: https://lore.kernel.org/r/20210107072538.21782-1-adrian.hunter@intel.com Reviewed-by: Avri Altman Reviewed-by: Bean Huo Reviewed-by: Can Guo Signed-off-by: Adrian Hunter Signed-off-by: Martin K. Petersen

scsi: ufs-qcom: Add Inline Crypto Engine support

2020-07-25T02:09:54+00:00

Add support for Qualcomm Inline Crypto Engine (ICE) to ufs-qcom. The standards-compliant parts, such as querying the crypto capabilities and enabling crypto for individual UFS requests, are already handled by ufshcd-crypto.c, which itself is wired into the blk-crypto framework. However, ICE requires vendor-specific init, enable, and resume logic, and it requires that keys be programmed and evicted by vendor-specific SMC calls. Make the ufs-qcom driver handle these details. I tested this on Dragonboard 845c, which is a publicly available development board that uses the Snapdragon 845 SoC and runs the upstream Linux kernel. This is the same SoC used in the Pixel 3 and Pixel 3 XL phones. This testing included (among other things) verifying that the expected ciphertext was produced, both manually using ext4 encryption and automatically using a block layer self-test I've written. I've also tested that this driver works nearly as-is on the Snapdragon 765 and Snapdragon 865 SoCs. And others have tested it on Snapdragon 850, Snapdragon 855, and Snapdragon 865 (see the Tested-by tags). This is based very loosely on the vendor-provided driver in the kernel source code for the Pixel 3, but I've greatly simplified it. Also, for now I've only included support for major version 3 of ICE, since that's all I have the hardware to test with the mainline kernel. Plus it appears that version 3 is easier to use than older versions of ICE. For now, only allow using AES-256-XTS. The hardware also declares support for AES-128-XTS, AES-{128,256}-ECB, and AES-{128,256}-CBC (BitLocker variant). But none of these others are really useful, and they'd need to be individually tested to be sure they worked properly. This commit also changes the name of the loadable module from "ufs-qcom" to "ufs_qcom", as this is necessary to compile it from multiple source files (unless we were to rename ufs-qcom.c). Link: https://lore.kernel.org/r/20200710072013.177481-6-ebiggers@kernel.org Tested-by: Steev Klimaszewski # Lenovo Yoga C630 Tested-by: Thara Gopinath # db845c, sm8150-mtp, sm8250-mtp Reviewed-by: Avri Altman Acked-by: Bjorn Andersson Signed-off-by: Eric Biggers Signed-off-by: Martin K. Petersen

scsi: ufs: UFS crypto API

2020-07-08T05:23:29+00:00

Introduce functions to manipulate UFS inline encryption hardware in line with the JEDEC UFSHCI v2.1 specification and to work with the block keyslot manager. The UFS crypto API will assume by default that a vendor driver doesn't support UFS crypto, even if the hardware advertises the capability, because a lot of hardware requires some special handling that's not specified in the aforementioned JEDEC spec. Each vendor driver must explicitly set hba->caps |= UFSHCD_CAP_CRYPTO before ufshcd_hba_init_crypto_capabilities() is called to opt-in to UFS crypto support. Link: https://lore.kernel.org/r/20200706200414.2027450-3-satyat@google.com Reviewed-by: Eric Biggers Reviewed-by: Stanley Chu Reviewed-by: Alim Akhtar Signed-off-by: Satya Tangirala Signed-off-by: Martin K. Petersen

scsi: ufs: ufs-exynos: Add UFS host support for Exynos SoCs

2020-06-15T18:04:10+00:00

This patch introduces Exynos UFS host controller driver which mainly handles vendor-specific operations including link startup, power mode change and hibernation/unhibernation. [robot: drivers/scsi/ufs/ufs-exynos.c:931:8-10: WARNING: possible condition with no effect (if == else) ] Link: https://lore.kernel.org/r/20200528011658.71590-10-alim.akhtar@samsung.com Reported-by: kbuild test robot Reported-by: Julia Lawall Tested-by: Paweł Chmiel Reviewed-by: Kiwoong Kim Reviewed-by: Avri Altman Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar Signed-off-by: Martin K. Petersen

scsi: ufs: Add driver for TI wrapper for Cadence UFS IP

2019-11-13T03:21:33+00:00

TI's J721e SoC has a Cadence UFS IP with a TI specific wrapper. This is a minimal driver to configure the wrapper. It releases the UFS slave device out of reset and sets up registers to indicate PHY reference clock input frequency before probing child Cadence UFS driver. Link: https://lore.kernel.org/r/20191108164857.11466-3-vigneshr@ti.com Reviewed-by: Avri Altman Reviewed-by: Alim Akhtar Signed-off-by: Vignesh Raghavendra Signed-off-by: Martin K. Petersen

scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips

2019-03-19T20:56:21+00:00

This patch adds UFS support for MediaTek SoC chips. Signed-off-by: Stanley Chu Reviewed-by: Avri Altman Signed-off-by: Martin K. Petersen