kernel/git/stable/linux.git/drivers/soc/imx/gpcv2.c, branch master

soc: imx: Move power-domain drivers to the genpd dir

2023-07-11T13:30:09+00:00

To simplify with maintenance let's move the imx power-domain drivers to the new genpd directory. Going forward, patches are intended to be managed through a separate git tree, according to MAINTAINERS. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Cc: Reviewed-by: Fabio Estevam Signed-off-by: Ulf Hansson

irqchip/irq-imx-gpcv2: Mark fwnode device as not initialized

2023-02-08T12:37:55+00:00

Since this device is only partially initialized by the irqchip driver, we need to mark the fwnode device as not initialized. This is to let fw_devlink know that the device will be completely initialized at a later point. That way, fw_devlink will continue to defer the probe of the power domain consumers till the power domain driver successfully binds to the struct device and completes the initialization of the device. Signed-off-by: Saravana Kannan Tested-by: Douglas Anderson Tested-by: Geert Uytterhoeven Tested-by: Luca Weiss # qcom/sm7225-fairphone-fp4 Link: https://lore.kernel.org/r/20230207014207.1678715-11-saravanak@google.com Signed-off-by: Greg Kroah-Hartman

soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/n

2022-10-29T08:20:49+00:00

To keep the power domain on if usb remote wakeup is enabled, add the GENPD_FLAG_ACTIVE_WAKEUP for otg1/2 of imx8mm/n. Signed-off-by: Li Jun Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: Assert reset before ungating clock

2022-08-21T13:34:48+00:00

In case the power domain clock are ungated before the reset is asserted, the system might freeze completely. This is likely due to a device is an undefined state being attached to bus, which sporadically leads to a bus hang. Assert the reset before the clock are enabled to assure the device is in defined state before being attached to bus. Fixes: fe58c887fb8ca ("soc: imx: gpcv2: add support for optional resets") Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: print errno for regulator errors

2022-06-19T07:14:39+00:00

Make debugging of power management issues easier by printing the reason why a regulator fails to be enabled or disabled. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo

soc: imx: gpcv2: add support for i.MX8MP power domains

2022-04-08T12:02:36+00:00

This adds driver support for all the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Tested-by: Laurent Pinchart Tested-by: Peng Fan Signed-off-by: Shawn Guo

soc: imx: gpcv2: add PGC control register indirection

2022-04-08T12:01:46+00:00

The PGC control registers in the shared (not per-PGC) region of the GPC address space have different offsets on i.MX8MP to make space for additional interrupt control registers. Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Tested-by: Peng Fan Signed-off-by: Shawn Guo

soc: imx: gpcv2: Fix clock disabling imbalance in error path

2022-02-21T07:27:41+00:00

The imx_pgc_power_down() starts by enabling the domain clocks, and thus disables them in the error path. Commit 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") made the clock enable conditional, but forgot to add the same condition to the error path. This can result in a clock enable/disable imbalance. Fix it. Fixes: 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") Signed-off-by: Laurent Pinchart Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn

2021-12-17T02:53:09+00:00

The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled

2021-12-17T02:53:03+00:00

Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo