kernel/git/stable/linux.git/drivers/spi/spi-rzv2h-rspi.c, branch master

Merge tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

2026-07-05T15:24:06+00:00

Pull spi fixes from Mark Brown: "A small set of fixes that came in since -rc1, we have one core fix for shutting down target mode properly if the system suspends while it's running plus a small set of fairly unremarkable device specific fixes. There's also a couple of pure DT binding changes for Renesas SoCs, the power domains one allows some SoCs to be correctly described with existing code" * tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: rzv2h-rspi: Fix DMA transfer error handling for signal interruption spi: dt-bindings: snps,dw-apb-ssi: add 'power-domains' property spi: dt-bindings: snps,dw-apb-ssi: drop superfluous RZ/N1 entry spi: dw: use the correct error msg if request_irq() fails spi: dw: fix first spi transfer with dma always fallback to PIO spi: core: Abort active target transfer on controller suspend spi: sh-msiof: abort transfers when reset times out

spi: rzv2h-rspi: Fix DMA transfer error handling for signal interruption

2026-06-30T18:58:20+00:00

wait_event_interruptible_timeout() can return a negative error code when interrupted by a signal. The original code treated all non-zero return values as success, which would incorrectly synchronize DMA channels and return 0 instead of propagating the interruption error. Fixes: fa08b566860b ("spi: rzv2h-rspi: add support for DMA mode") Signed-off-by: Felix Gu Reviewed-by: Cosmin Tanislav Tested-by: Cosmin Tanislav Reviewed-by: Wolfram Sang Link: https://patch.msgid.link/20260627-rspi-v1-1-170c93ee14da@gmail.com Signed-off-by: Mark Brown

Merge tag 'spi-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

2026-06-16T02:26:47+00:00

Pull spi updates from Mark Brown: "This has been quite a busy release, mainly due to the subsystem wide work Johan Hovold has done to modernise resource allocation for the subsystem on probe, the subsystem did some very clever allocation management pre devm which didn't quite mesh comfortably with managed allocations and made it far too easy to introduce error handling and removal bugs. - Cleanup and simplification of controller struct allocation, moving everything over to devm and making the devm APIs more robust, from Johan Hovold - Support for spi-mem devices that don't assert chip select and support for a secondary read command for memory mapped flashes, some commits for this are shared with mtd. - Support for SpacemiT K1" * tag 'spi-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (118 commits) spi: Fix mismatched DT property access types spi: xilinx: use FIFO occupancy register to determine buffer size spi: spi-mem: Fix spi_controller_mem_ops kdoc spi: xilinx: let transfers timeout in case of no IRQ spi: dt-bindings: nuvoton,npcm750-fiu: Convert to DT schema spi: meson-spifc: fix runtime PM leak on remove spi: Use named initializers for platform_device_id arrays spi: rzv2h-rspi: Add suspend/resume support spi: dw-pci: remove redundant pci_free_irq_vectors() calls spi: ep93xx: fix double-free of zeropage on DMA setup failure spi: cadence-xspi: Revert COMPILE_TEST support spi: cadence-xspi: Support 32bit and 64bit slave dma interface spi: tegra210-quad: Allocate DMA memory for DMA engine spi: imx: replace dmaengine_terminate_all() with dmaengine_terminate_sync() spi: fsl-lpspi: terminate the RX channel on TX prepare failure path spi: fsl-lpspi: replace dmaengine_terminate_all() with dmaengine_terminate_sync() spi: atmel: fix DMA channel and bounce buffer leaks spi: omap2-mcspi: Use of_device_get_match_data() spi: Use named initializers for arrays of i2c_device_data spi: aspeed: Replace VLA parameter with flat pointer in calibration helper ...

spi: rzv2h-rspi: Fix SPDR read access width for 16-bit RX

2026-06-10T15:39:13+00:00

The RZ/V2H hardware manual (section 7.5.2.2.1) specifies that read access size for the SPI Data Register (SPDR) are fixed at 32 bits. The RZV2H_RSPI_RX macro for the 16-bit data path used readw(), violating this requirement. Switch to readl() for the 16-bit RX path to conform to the hardware specification. Fixes: 8b61c8919dff ("spi: Add driver for the RZ/V2H(P) RSPI IP") Suggested-by: Geert Uytterhoeven Signed-off-by: Felix Gu Reviewed-by: Geert Uytterhoeven Reviewed-by: Fabrizio Castro Link: https://patch.msgid.link/20260610-rzv2h-rspi-v2-1-40c80b4a2c90@gmail.com Signed-off-by: Mark Brown

spi: rzv2h-rspi: Add suspend/resume support

2026-06-09T21:43:17+00:00

Add suspend/resume support to the rzv2h-rspi driver by implementing suspend and resume callbacks that delegate to spi_controller_suspend() and spi_controller_resume() respectively. Signed-off-by: Tommaso Merciai Link: https://patch.msgid.link/20260608202509.3651345-1-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Mark Brown

spi: rzv2h-rspi: Fix silent failure in clock setup error path

2026-04-26T21:45:08+00:00

rzv2h_rspi_setup_clock() is declared to return u32 but returns -EINVAL when no valid clock parameters are found. Cast to u32, -EINVAL becomes 0xffffffea, which is a non-zero value. The caller in rzv2h_rspi_prepare_message() guards against failure with: rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz); if (!rspi->freq) return -EINVAL; Because 0xffffffea is non-zero, the check is bypassed and the controller proceeds to program SPBR/SPCMD with stale values, leading to an unknown bit rate. Return 0 on the failed-search path, consistent with the existing clk_set_rate() failure path which already returns 0. Fixes: 77d931584dd3 ("spi: rzv2h-rspi: make transfer clock rate finding chip-specific") Signed-off-by: John Madieu Reviewed-by: Biju Das Reviewed-by: Cosmin Tanislav Link: https://patch.msgid.link/20260425024725.2393632-1-john.madieu.xa@bp.renesas.com Signed-off-by: Mark Brown

spi: rzv2h-rspi: Fix max_speed_hz and clock configuration issues

2026-04-10T12:20:01+00:00

Prabhakar says: This patch series addresses three issues in the RZV2H RSPI driver: 1. The max_speed_hz field was advertising a prohibited bit rate, which could lead to incorrect behavior when userspace applications attempt to set the SPI clock speed. 2. The clock configuration logic allowed for an invalid combination of SPR=0 and BRDV=0, which is not supported by the hardware. 3. Simplified the clock rate search function as min/max speed parameters are not needed. Note, patches apply on top of next-20260409.

spi: rzv2h-rspi: Simplify clock rate search function signatures

2026-04-10T12:20:00+00:00

The spr_min and spr_max parameters passed to rzv2h_rspi_find_rate_variable() and rzv2h_rspi_find_rate_fixed() were always called with RSPI_SPBR_SPR_MIN and RSPI_SPBR_SPR_MAX respectively. There is no need to pass these as parameters since the valid SPR range is fixed by the hardware. Signed-off-by: Lad Prabhakar Link: https://patch.msgid.link/20260410080517.2405700-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown

spi: rzv2h-rspi: Fix invalid SPR=0/BRDV=0 clock configuration

2026-04-10T12:19:59+00:00

The combination of SPR=0 and BRDV=0 results in the minimum division ratio of 2, producing the maximum possible bit rate for a given clock source. This combination is not supported in two cases: - On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is fixed at 200MHz, which would yield 100Mbps. The next hardware manual update will explicitly state that since the maximum frequency of the RSPICKn clock signal is 50MHz, settings with N=0 and n=0 resulting in 100Mbps are prohibited. - On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as the clock source, SPR=0 and BRDV=0 is explicitly listed as unsupported in the hardware manual (Table 36.7). Skip the SPR=0/BRDV=0 combination in rzv2h_rspi_find_rate_fixed() to prevent the driver from selecting an invalid clock configuration on the affected SoCs. Additionally, remove the now redundant RSPI_SPBR_SPR_PCLK_MIN define which was previously set to 1 to work around the PCLK restriction, but was overly broad as it incorrectly blocked valid combinations such as SPR=0/BRDV=1 (31.25Mbps on PCLK=125MHz). Fixes: 8b61c8919dff ("spi: Add driver for the RZ/V2H(P) RSPI IP") Fixes: 1ce3e8adc7d0 ("spi: rzv2h-rspi: add support for using PCLK for transfer clock") Signed-off-by: Lad Prabhakar Link: https://patch.msgid.link/20260410080517.2405700-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown

spi: rzv2h-rspi: Fix max_speed_hz advertising prohibited bit rate

2026-04-10T12:19:58+00:00

On RZ/V2H(P), RZ/G3E and RZ/G3L, RSPI_n_TCLK is fixed at 200MHz. The max_speed_hz was computed using clk_round_rate(tclk, ULONG_MAX) with SPR=0 and BRDV=0, resulting in 100Mbps - the exact combination prohibited on these SoCs. This could cause the SPI framework to request a speed that rzv2h_rspi_find_rate_fixed() would skip, potentially leading to a clock selection failure. On RZ/T2H and RZ/N2H the max_speed_hz was correctly calculated as 50Mbps for both the variable PCLKSPIn and fixed PCLK clock sources. Since the maximum supported bit rate is 50Mbps across all supported SoC variants, replace the clk_round_rate() based calculation with a define RSPI_MAX_SPEED_HZ set to 50MHz and use it directly for max_speed_hz. Signed-off-by: Lad Prabhakar Link: https://patch.msgid.link/20260410080517.2405700-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown