kernel/git/stable/linux.git/drivers/thunderbolt/nhi_ops.c, branch master

thunderbolt: Separate out common NHI bits

2026-05-21T12:29:05+00:00

Add a new file encapsulating most of the PCI NHI specifics (intentionally leaving some odd cookies behind to make the layering simpler). Most notably, separate out nhi_probe() to make it easier to register other types of NHIs. Also, fold in Intel Icelake (nhi_ops.c) support to contain all PCIe-related bits in pci.c. Signed-off-by: Konrad Dybcio Signed-off-by: Mika Westerberg

thunderbolt: Move pci_device out of tb_nhi

2026-05-21T12:29:05+00:00

Not all USB4/TB implementations are based on a PCIe-attached controller. In order to make way for these, start off with moving the pci_device reference out of the main tb_nhi structure. Encapsulate the existing struct in a new tb_nhi_pci, that shall also house all properties that relate to the parent bus. Similarly, any other type of controller will be expected to contain tb_nhi as a member. Signed-off-by: Konrad Dybcio Signed-off-by: Mika Westerberg

thunderbolt: Software CM only should set force power in Tiger Lake

2020-09-03T09:06:40+00:00

When Software CM is running it should not send any NHI mailbox command during PM flows. Only force power bit needs to be set and cleared so change Tiger Lake (well and Ice Lake) nhi_ops to take this into account. Signed-off-by: Mika Westerberg

thunderbolt: Optimize NHI LC mailbox command processing

2020-09-03T09:06:40+00:00

Currently the Ice Lake and Tiger Lake NHI (host controller) LC (link controller) mailbox command processing checks for the completion of command every 100 msecs. These controllers are found to complete this in the order of 1 ms or so. Since this delay is in suspend path, surplus delay is effectively affecting runtime PM suspend flows. Optimize this so that we do the wait for 1 ms after reading the mailbox register. This should make Ice Lake and Tiger Lake runtime suspend take less time to complete. Reported-by: Dana Alkattan Signed-off-by: Rajmohan Mani Signed-off-by: Mika Westerberg

thunderbolt: Optimize Force Power logic

2020-09-03T09:06:40+00:00

Currently the "Force Power" logic uses 10 retries, each with a delay of 250 ms. Thunderbolt controllers in Ice Lake and Tiger Lake platforms are found to complete this in the order of 3 ms or so. Since this delay is in resume path, surplus delay is effectively affecting runtime PM resume flows. Decrease the granularity of the delay to 3 ms and increase the number of retries so we wait maximum of ~1 s which is the recommended timeout. This should make runtime resume a bit faster. Reported-by: Dana Alkattan Signed-off-by: Rajmohan Mani Signed-off-by: Mika Westerberg

thunderbolt: Drop unnecessary read when writing LC command in Ice Lake

2019-10-08T09:08:21+00:00

The read is not needed as we overwrite the returned value in the next line anyway so drop it. Fixes: 3cdb9446a117 ("thunderbolt: Add support for Intel Ice Lake") Reported-by: Nicholas Johnson Signed-off-by: Mika Westerberg

thunderbolt: Add support for Intel Ice Lake

2019-08-26T09:15:06+00:00

The Thunderbolt controller is integrated into the Ice Lake CPU itself and requires special flows to power it on and off using force power bit in NHI VSEC registers. Runtime PM (RTD3) and Sx flows also differ from the discrete solutions. Now the firmware notifies the driver whether RTD3 entry or exit are possible. The driver is responsible of sending Go2Sx command through link controller mailbox when system enters Sx states (suspend-to-mem/disk). Rest of the ICM firwmare flows follow Titan Ridge. Signed-off-by: Raanan Avargil Signed-off-by: Mika Westerberg Reviewed-by: Yehezkel Bernat Tested-by: Mario Limonciello