<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/include/asm-ia64/sal.h, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master'/>
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<updated>2008-08-01T17:21:21+00:00</updated>
<entry>
<title>[IA64] Move include/asm-ia64 to arch/ia64/include/asm</title>
<updated>2008-08-01T17:21:21+00:00</updated>
<author>
<name>Tony Luck</name>
<email>tony.luck@intel.com</email>
</author>
<published>2008-08-01T17:13:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=7f30491ccd28627742e37899453ae20e3da8e18f'/>
<id>urn:sha1:7f30491ccd28627742e37899453ae20e3da8e18f</id>
<content type='text'>
After moving the the include files there were a few clean-ups:

1) Some files used #include &lt;asm-ia64/xyz.h&gt;, changed to &lt;asm/xyz.h&gt;

2) Some comments alerted maintainers to look at various header files to
make matching updates if certain code were to be changed. Updated these
comments to use the new include paths.

3) Some header files mentioned their own names in initial comments. Just
deleted these self references.

Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] Kernel parameter for max number of concurrent global TLB purges</title>
<updated>2008-04-04T18:06:38+00:00</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2008-03-14T20:57:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a6c75b86ce9f01db4ea9912877b526c2dc4d2f0a'/>
<id>urn:sha1:a6c75b86ce9f01db4ea9912877b526c2dc4d2f0a</id>
<content type='text'>
The patch defines kernel parameter "nptcg=". The parameter overrides max number
of concurrent global TLB purges which is reported from either PAL_VM_SUMMARY or
SAL PALO.

Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] Multiple outstanding ptc.g instruction support</title>
<updated>2008-04-04T18:05:59+00:00</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2008-04-04T18:05:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=2046b94e7c4fce92eb8165c2c36c6478f4927178'/>
<id>urn:sha1:2046b94e7c4fce92eb8165c2c36c6478f4927178</id>
<content type='text'>
According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions.
But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize
ptc.g instructions issued by multiple processors. This serialization might have
scalability issue on a big SMP machine where many processors could purge TLB
in parallel.

The patch fixes this problem by issuing multiple ptc.g instructions in
ia64_global_tlb_purge(). It also adds support for the "PALO" table to get
a platform view of the max number of outstanding ptc.g instructions (which
may be different from the processor view found from PAL_VM_SUMMARY).

PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf

spinaphore implementation by Matthew Wilcox.

Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] workaround tiger ia64_sal_get_physical_id_info hang</title>
<updated>2008-03-04T22:26:50+00:00</updated>
<author>
<name>Alex Chiang</name>
<email>achiang@hp.com</email>
</author>
<published>2008-02-28T01:41:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=6ed0dc5ba811ce682f48988bf114669265e1120d'/>
<id>urn:sha1:6ed0dc5ba811ce682f48988bf114669265e1120d</id>
<content type='text'>
This fixes regression introduced in 113134fcbca83619be4c68d0ca66db6093777b5d

Intel Tiger platforms hang when calling SAL_GET_PHYSICAL_ID_INFO
instead of properly returning -1 for unimplemented, so add a
version check.

SGI Altix platforms have an incorrect SAL version hard-coded into
their prom -- they encode 2.9, but actually implement 3.2 -- so
fix it up and allow ia64_sal_get_physical_id_info to keep
working.

Signed-off-by: Alex Chiang &lt;achiang@hp.com&gt;
Acked-by: Russ Anderson &lt;rja@sgi.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] Export three symbols for module use</title>
<updated>2008-02-04T23:46:23+00:00</updated>
<author>
<name>Zhang, Xiantao</name>
<email>xiantao.zhang@intel.com</email>
</author>
<published>2008-02-04T23:46:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a7d57ecf4216ed29328f8e701bd65ebb66a0284c'/>
<id>urn:sha1:a7d57ecf4216ed29328f8e701bd65ebb66a0284c</id>
<content type='text'>
Since kvm/module needs to use some unexported functions in kernel,
so export them with this patch.

Signed-off-by: Zhang Xiantao &lt;xiantao.zhang@intel.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] abstract SAL_CALL wrapper to allow other firmware entry points</title>
<updated>2007-10-12T22:11:22+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bjorn.helgaas@hp.com</email>
</author>
<published>2007-09-20T20:21:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=edbe7075d144b35e8232ca32f373c1e0c26ff085'/>
<id>urn:sha1:edbe7075d144b35e8232ca32f373c1e0c26ff085</id>
<content type='text'>
SAL_CALL() always calls through the ia64_sal function pointer.  I am adding
new functionality that needs the same conventions as SAL_CALL (FP regs
saved/restored, sal_lock acquired, etc), but doesn't use the ia64_sal
function pointer.

This patch pulls the body of SAL_CALL out into a new "IA64_FW_CALL" that
takes care of these calling conventions, but allows the caller to specify
either ia64_sal or some other firmware entry point.

Signed-off-by: Bjorn Helgaas &lt;bjorn.helgaas@hp.com&gt;
Signed-off-by: Len Brown &lt;len.brown@intel.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] whitespace fixes for include/asm-ia64/sal.h</title>
<updated>2007-03-08T17:58:13+00:00</updated>
<author>
<name>Horms</name>
<email>horms@verge.net.au</email>
</author>
<published>2007-02-07T06:49:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=860abe8f7254208074cef83dc9ebc4d70ae277a9'/>
<id>urn:sha1:860abe8f7254208074cef83dc9ebc4d70ae277a9</id>
<content type='text'>
* Make use of spaces and tabs consistent
* Make long line &lt; 80col

Signed-off-by: Simon Horman &lt;horms@verge.net.au&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] move SAL_CACHE_FLUSH check later in boot</title>
<updated>2006-10-31T22:32:10+00:00</updated>
<author>
<name>Troy Heber</name>
<email>troy.heber@hp.com</email>
</author>
<published>2006-10-25T20:46:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=fa1d19e5d9a94120f31e5783ab44758f46892d94'/>
<id>urn:sha1:fa1d19e5d9a94120f31e5783ab44758f46892d94</id>
<content type='text'>
The check to see if the firmware drops interrupts during a
SAL_CACHE_FLUSH is done to early in the boot. SAL_CACHE_FLUSH expects
to be able to make PAL calls in virtual mode, on some cell based
machines a fault occurs causing a MCA. This patch moves the check
after mmu_context_init so the TLB and VHPT are properly setup.

Signed-off-by Troy Heber &lt;troy.heber@hp.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] avoid broken SAL_CACHE_FLUSH implementations</title>
<updated>2006-02-02T21:25:54+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bjorn.helgaas@hp.com</email>
</author>
<published>2006-01-30T23:32:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a58786917ce23c2a26c3e099c3cdba32a35eeceb'/>
<id>urn:sha1:a58786917ce23c2a26c3e099c3cdba32a35eeceb</id>
<content type='text'>
If SAL_CACHE_FLUSH drops interrupts, complain about it and fall back to
using PAL_CACHE_FLUSH instead.

This is to work around a defect in HP rx5670 firmware: when an interrupt
occurs during SAL_CACHE_FLUSH, SAL drops the interrupt but leaves it marked
"in-service", which leaves the interrupt (and others of equal or lower
priority) masked.

Signed-off-by: Bjorn Helgaas &lt;bjorn.helgaas@hp.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
<entry>
<title>[IA64] Split 16-bit severity field in sal_log_record_header</title>
<updated>2005-12-13T18:41:49+00:00</updated>
<author>
<name>Tony Luck</name>
<email>tony.luck@intel.com</email>
</author>
<published>2005-12-13T18:41:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=eed66cfcbbea851c97e287440d940286fce3f829'/>
<id>urn:sha1:eed66cfcbbea851c97e287440d940286fce3f829</id>
<content type='text'>
ERR_SEVERITY item is defined as a 8 bits item in SAL documentation
($B.2.1 rev december 2003), but as an u16 in sal.h.
This has the side effect that current code in mca.c may not call
ia64_sal_clear_state_info() upon receiving corrected platform errors
if there are bits set in the validation byte.  Reported by Xavier Bru.

Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
</content>
</entry>
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