kernel/git/stable/linux.git/include/asm-sh/system.h, branch linux-2.6.21.y

sh: Fixup __cmpxchg() compile breakage with gcc4.

2007-03-28T08:26:19+00:00

As reported by Manuel: When I build linux with GCC-4.x and enable CONFIG_CC_OPTIMIZE_FOR_SIZE linking fails with this error: LD .tmp_vmlinux1 kernel/built-in.o: In function '__cmpxchg_called_with_bad_pointer' make[1]: *** [.tmp_vmlinux1] Error 1 make: *** [_all] Error 2 This ended up being an inlining problem, fixed by explicitly including linux/compiler.h and grabbing the definitions from there. Signed-off-by: Paul Mundt

sh: stacktrace/lockdep/irqflags tracing support.

2006-12-06T01:45:40+00:00

Wire up all of the essentials for lockdep.. Signed-off-by: Paul Mundt

sh: Fix exception_handling_table alignment.

2006-10-19T07:30:32+00:00

With the recent change ripping out interrupt_table, explicit padding of the table was missing, causing bad things to happen when manually inserting handlers in to the table. This problem particularly showed up in relation to do_fpu_state_restore() which was inserted quite deeply in to the table and ended up scribbling over a slab object. Signed-off-by: Paul Mundt

sh: More cosmetic cleanups and trivial fixes.

2006-09-27T08:03:56+00:00

Nothing exciting here, just trivial fixes.. Signed-off-by: Paul Mundt

sh: APM/PM support.

2006-09-27T07:20:22+00:00

This adds some simple PM stubs and the basic APM interfaces, primarily for use by hp6xx, where the existing userland expects it. Signed-off-by: Andriy Skulysh Signed-off-by: Paul Mundt

sh: xchg()/__xchg() always_inline fixes for gcc4.

2006-09-27T07:05:56+00:00

Make __xchg() a macro, so that gcc 4.0 doesn't blow up thanks to always_inline.. Signed-off-by: Paul Mundt

sh: Cleanup and document register bank usage.

2006-09-27T07:01:12+00:00

Initial register bank cleanup. Make SR.RB configurable, and add some preliminary documentation on register bank usage within the kernel. Signed-off-by: Paul Mundt

sh: Add control register barriers.

2006-09-27T05:57:44+00:00

Currently when making changes to control registers, we typically need some time for changes to take effect (8 nops, generally). However, for sh4a we simply need to do an icbi.. This is a simple patch for implementing a general purpose ctrl_barrier() which functions as a control register write barrier. There's some additional documentation in the patch itself, but it's pretty self explanatory. There were also some places where we were not doing the barrier, which didn't seem to have any adverse effects on legacy parts, but certainly did on sh4a. It's safer to have the barrier in place for legacy parts as well in these cases, though this does make flush_tlb_all() more expensive (by an order of 8 nops). We can ifdef around the flush_tlb_all() case for now if it's clear that all legacy parts won't have a problem with this. Signed-off-by: Paul Mundt

sh: Support for SH-4A memory barriers.

2006-09-27T05:05:52+00:00

SH-4A supports 'synco' as a barrier, sprinkle it around the cache ops as necessary.. Signed-off-by: Paul Mundt

sh: Add a simple cmpxchg().

2006-09-27T02:28:20+00:00

We didn't have one of these before, a simple implementation borrowed from MIPS as well as the __HAVE_ARCH_CMPXCHG bits. Signed-off-by: Tom Rini Signed-off-by: Paul Mundt