kernel/git/stable/linux.git/include/asm-sparc64/tsb.h, branch master

sparc, sparc64: use arch/sparc/include

2008-07-27T21:00:59+00:00

The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg

sparc: copy sparc64 specific files to asm-sparc

2008-07-18T04:44:53+00:00

Used the following script to copy the files: cd include set -e SPARC64=`ls asm-sparc64` for FILE in ${SPARC64}; do if [ -f asm-sparc/$FILE ]; then echo $FILE exist in asm-sparc else git mv asm-sparc64/$FILE asm-sparc/$FILE printf "#include \n" > asm-sparc64/$FILE git add asm-sparc64/$FILE fi done Signed-off-by: Sam Ravnborg

[SPARC64]: Fix two bugs wrt. kernel 4MB TSB.

2007-05-29T09:51:38+00:00

1) The TSB lookup was not using the correct hash mask. 2) It was not aligned on a boundary equal to it's size, which is required by the sun4v Hypervisor. wasn't having it's return value checked, and that bug will be fixed up as well in a subsequent changeset. Signed-off-by: David S. Miller

[SPARC64]: Get DEBUG_PAGEALLOC working again.

2007-03-17T00:20:28+00:00

We have to make sure to use base-pagesize TLB entries even during the early transition period where we need TLB miss handling but don't have the kernel page tables setup yet for the linear region. Also, it is necessary therefore to not use the 4MB TSB for these translations, and instead use the normal kernel TSB. This allows us to also get rid of the 4MB tsb for debug builds which shrinks the kernel a little bit. Signed-off-by: David S. Miller

[SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.

2006-03-20T09:13:56+00:00

It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller

[SPARC64]: More TLB/TSB handling fixes.

2006-03-20T09:13:34+00:00

The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller

[SPARC64]: Initial sun4v TLB miss handling infrastructure.

2006-03-20T09:11:52+00:00

Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller

[SPARC64]: Access TSB with physical addresses when possible.

2006-03-20T09:11:32+00:00

This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller

[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h

2006-03-20T09:11:31+00:00

Signed-off-by: David S. Miller

[SPARC64]: Increase swapper_tsb size to 32K.

2006-03-20T09:11:26+00:00

Signed-off-by: David S. Miller