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2026-07-07arm64: dts: qcom: sdm670-google: add lpi reserved gpiosRichard Acayan
Add reserved GPIOs for the Pixel 3a, which blocks access to the sensor GPIOs. The hunk in the original patch was dropped in the commit because it depended on an unapplied patch, which is now commit fe9f4a46895d ("arm64: dts: qcom: sdm670-google: add common device tree include"). Fixes: c4b423835ee7 ("arm64: dts: qcom: sdm670: add lpi pinctrl") Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260602021722.30760-1-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: ipq5424: Move PHYs and PERST# to Root Port nodeKathiravan Thirumoorthy
Follow the new binding style by defining PHYs and PERST# (now RESET#) under the Root Port node. Avoid mixing styles and move these properties to the RP node. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-move_perst_to_rp-v2-2-6c731523d08c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: ipq5332: Move PHYs and PERST# to Root Port nodeKathiravan Thirumoorthy
Follow the new binding style by defining PHYs and PERST# (now RESET#) under the Root Port node. Avoid mixing styles and move these properties to the RP node. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-move_perst_to_rp-v2-1-6c731523d08c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: eliza: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on eliza spans 0x10000 bytes. Reduce the size of the first reg entry from 0x40000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-25-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: qdu1000: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on qdu1000 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-24-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: milos: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on milos spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-23-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sdx75: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sdx75 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-22-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: lemans: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on lemans spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-21-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: monaco: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on monaco spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-20-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: talos: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on talos spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-19-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sar2130p: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sar2130p spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-18-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm6350: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm6350 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-17-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: x1e80100: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on x1e80100 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-16-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm4450: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm4450 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-15-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm8650: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm8650 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-14-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm8550: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm8550 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-13-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm8450: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm8450 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-12-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm8350: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm8350 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-11-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm8250: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm8250 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-10-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sc8280xp spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-9-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sm8150: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sm8150 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-8-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8180x: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sc8180x spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-7-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc7280: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sc7280 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-6-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc7180: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sc7180 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-5-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sdm670: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sdm670 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-4-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sdm845: Reduce OS PDC DRV span to 0x10000Mukesh Ojha
The OS PDC DRV register window on sdm845 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260527094333.2311731-3-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07hwmon: (corsair-psu) Stop device IO before calling hid_hw_stopEdward Adam Davis
hid_hw_stop() does not stop the device IO. This results in a race condition between hid_input_report() and the point immediately following the execution of hid_device_io_start() within corsairpsu_probe(). If the probe operation fails after "io start" has been initiated, this race condition will result in a uaf vulnerability [1]. CPU0 CPU1 ==== ==== corsairpsu_probe() hid_device_io_start() ... unlock driver_input_lock hid_hw_stop() kfree(hidraw) __hid_input_report() ... acquire driver_input_lock hid_report_raw_event() hidraw_report_event() ... access hidraw's list_lock // trigger uaf Consequently, when corsairpsu_probe() fails and hid_hw_stop() needs to be executed, the io_started flag is first cleared while holding the driver_input_lock to prevent potential race conditions involving input reports. [1] BUG: KASAN: slab-use-after-free in rt_spin_lock+0x83/0x400 kernel/locking/spinlock_rt.c:56 Call Trace: hidraw_report_event+0x5d/0x3a0 drivers/hid/hidraw.c:577 hid_report_raw_event+0x311/0x1730 drivers/hid/hid-core.c:2076 __hid_input_report drivers/hid/hid-core.c:2152 [inline] hid_input_report+0x44e/0x580 drivers/hid/hid-core.c:2174 hid_irq_in+0x47e/0x6d0 drivers/hid/usbhid/hid-core.c:286 __usb_hcd_giveback_urb+0x3b3/0x5e0 drivers/usb/core/hcd.c:1657 dummy_timer+0x8a9/0x47d0 drivers/usb/gadget/udc/dummy_hcd.c:2005 Allocated by task 10: hidraw_connect+0x57/0x430 drivers/hid/hidraw.c:606 hid_connect+0x5bf/0x19d0 drivers/hid/hid-core.c:2277 hid_hw_start+0xa8/0x120 drivers/hid/hid-core.c:2387 corsairpsu_probe+0xd9/0x3c0 drivers/hwmon/corsair-psu.c:782 Freed by task 10: hidraw_disconnect+0x4f/0x60 drivers/hid/hidraw.c:662 hid_disconnect drivers/hid/hid-core.c:2362 [inline] hid_hw_stop+0x101/0x1e0 drivers/hid/hid-core.c:2407 corsairpsu_probe+0x327/0x3c0 drivers/hwmon/corsair-psu.c:826 Fix the problem by calling hid_device_io_stop() before calling hid_hw_stop(). Fixes: d115b51e0e56 ("hwmon: add Corsair PSU HID controller driver") Reported-by: syzbot+9eebf5f6544c5e873858@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=9eebf5f6544c5e873858 Tested-by: syzbot+9eebf5f6544c5e873858@syzkaller.appspotmail.com Signed-off-by: Edward Adam Davis <eadavis@qq.com> Link: https://lore.kernel.org/r/tencent_BB7C33EB9EA41B7B4B5F1B8B25C0BA13BB08@qq.com [groeck: Updated subject and description; call hid_device_io_stop() only if IO has been started] Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2026-07-07arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Fixup panel compatibleYedaya Katsman
The change to the panel compatible was missed, fix it. This compatible is already in the driver. Fixes: 493cb869874c ("arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Enable MDSS and add panel") Signed-off-by: Yedaya Katsman <yedaya.ka@gmail.com> Reviewed-by: David Heidelberg <david@ixit.cz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-b4-compatible-s6e8fc0-fixup-v2-1-d23f373603a3@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Drop duplicate DMIC suppliesJérôme de Bretagne
Align with the reference implementation from the ThinkPad X13s. The audio-routing setup specifies two power supplies for each DMIC, but only one of them can be active at the same time. Drop the redundant routes to the pull-up "VA MIC BIASn" supplies as done in commit a2e617f4e698 ("arm64: dts: qcom: sc8280xp-x13s: Drop duplicate DMIC supplies"). There is no functional difference except that we skip briefly switching to pull-up mode when shutting down the microphone. Cc: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-10-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Switch to uefi rtc offsetJérôme de Bretagne
Align with the reference implementation from the ThinkPad X13s: Switch to using the Qualcomm specific UEFI variable that is used by the UEFI firmware (and Windows) to store the RTC offset. Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is stored in a UEFI variable so that the OS can determine whether to wait for it to become available. Cc: Johan Hovold <johan@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-9-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: model the PMU of the on-board wcn6855Jérôme de Bretagne
Align the Surface Pro 9 5G with the other sc8280xp-based models as done in this patch series [1] from Bartosz. Add a node for the PMU of the WCN6855 and rework the inputs of the wifi and bluetooth nodes to consume the PMU's outputs. With this we can drop the regulator-always-on properties from vreg_s11b and vreg_s12b as they will now be enabled by the power sequencing driver. Use the fixed BT vddrfa1p7-supply supply name to align with bindings. [1] https://lore.kernel.org/all/20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org/ Cc: Bartosz Golaszewski <brgl@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/all/20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org/ Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-8-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Add lid switchJérôme de Bretagne
Enable the lid switch for the Microsoft Surface Pro 9 5G using GPIO pin 180. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-7-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Add volume up/down GPIO keysJérôme de Bretagne
Configure gpio6 to serve as volume down and gpio9 as volume up to enable the volume up/down keys located at the top of the screen. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-6-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Enable 4-lane DP supportJérôme de Bretagne
Allow up to 4 lanes for the DisplayPort link from the PHYs to the controllers and allow mode-switch events to reach the QMP Combo PHYs for the 2 left-side USB-C ports. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-5-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Fix top USB-C DP alt modeJérôme de Bretagne
The top USB-C port (usb0) didn't switch to DP alt mode, as reusing the same GPIO 101 as on the SC8280XP CRD or Lenovo ThinkPad X13s was not working on the Surface Pro 9 5G. Investigation [1] by Jens on the Windows Dev Kit (WDK2023), the other sc8280xp-based "blackrock" model from Microsoft, found a reference to GPIO 100 in the DSDT in addition to 101. Switching to GPIO 100 fixed the issue on blackrock, as it does on arcata to enable external screen when using the left-side top USB-C port. [1] https://lore.kernel.org/all/20250609-blackrock-usb0-mux-v1-1-7903c3b071e4@oldschoolsolutions.biz/ Cc: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Fixes: f6231a2eefd4 ("arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5G") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-4-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: add USB-C orientation GPIOsJérôme de Bretagne
Define the USB-C orientation GPIOs so that the orientation is known for the two USB-C ports on the left-side. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-3-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Enable the eDP displayJérôme de Bretagne
Add the vreg_edp_3p3, edp_reg_en and mdss0_dp3 nodes to enable the Surface Pro 9 5G eDP-based LCD display (LG LP129WT232166). Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-2-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: sc8280xp-arcata: Enable backlightJérôme de Bretagne
Add backlight nodes and enable backlight so that it can be controlled with the corresponding buttons found on Surface Pro Type Cover keyboards. Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-1-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: monaco-arduino-monza: Add fan controller and thermal coolingLoic Poulain
Enable the CCI1 bus and add support for the Microchip EMC2305 fan controller on the Monaco Arduino Monza board. The controller is virtually implemented by the onboard MCU. Add a new active trip point to the cpuss0 thermal zone and associate it with onboard fan cooling. The CPU subsystem sensor is used as the thermal reference until support for a more appropriate onboard/skin sensor becomes available (via spmi-adc5-gen3). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609091206.522331-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07RAS/AMD/ATL, EDAC/amd64: Only load ATL when neededYazen Ghannam
The AMD Address Translation Library (ATL) will attempt to load on all AMD Zen/SMCA systems. However, only systems with DRAM ECC enabled will use the library. Other systems will fail to load the library and produce an unnecessary message to the user. More importantly, that thing is dead code loaded and unused. Remove the ATL module dependency table to prevent autoloading. Request ATL to load from EDAC once all system checks are complete. [ bp: Massage commit message. ] Fixes: 3f3174996be6 ("RAS: Introduce AMD Address Translation Library") Closes: https://lore.kernel.org/20260305154528.1171999-1-mario.limonciello@amd.com Reported-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Deskhmukh Shrirang <Shrirang.Deskhmukh@amd.com> Link: https://lore.kernel.org/all/20260307144910.GA113343@yaz-khff2.amd.com
2026-07-07arm64: dts: qcom: msm8996: add blsp2_spi5 nodeChristopher Obbard
Add the blsp2_spi5 SPI controller node together with its default and sleep pinctrl states. Signed-off-by: Christopher Obbard <christopher.obbard@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260508-wip-obbardc-msm8996-blsp2_spi4-v2-1-8b81a95b1ed7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: x1e80100: Add CAMCC block definitionBryan O'Donoghue
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. And update the compatible for camcc and videocc nodes on Purwa to match with their respective Purwa (X1P42100) specific drivers. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-6-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07ARM: dts: qcom: msm8960: expressatt: Add coreriver,tc360-touchkeyRudraksha Gupta
Add the tc360 touchkey. It's unknown if this is the actual model of the touchkey, as downstream doesn't mention a variant, but this works. Link: https://github.com/LineageOS/android_kernel_samsung_d2/blob/stable/cm-12.0-YNG4N/drivers/input/keyboard/cypress_touchkey_236/Makefile#L5 Assisted-by: Claude:claude-opus-4.6 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Rudraksha Gupta <guptarud@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://github.com/LineageOS/android_kernel_samsung_d2/blob/stable/cm-12.0-YNG4N/drivers/input/keyboard/cypress_touchkey_236/Makefile#L5 Link: https://lore.kernel.org/r/20260527-expressatt-touchkey-v2-1-049dca41fc3a@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07soc: qcom: pd-mapper: Add support for QCS8300Mohammad Rafi Shaik
Add support for the Qualcomm QCS8300 SoC to the protection domain mapper. QCS8300 share the same protection domain configuration as SC8280XP, except charger_pd. Add an entry to the kernel, to avoid the need for userspace to provide this service. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608084139.1468000-3-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07soc: qcom: pd-mapper: Add support for SA8775PMohammad Rafi Shaik
Add support for the Qualcomm SA8775P SoC to the protection domain mapper. SA8775P share the same protection domain configuration as SC8280XP with an additional gpdsp domain, except for charger_pd. Add an entry to the kernel, to avoid the need for userspace to provide this service. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608084139.1468000-2-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07soc: qcom: llcc: Add configuration data for Shikra SoCKomal Bajaj
Add Last Level Cache table and configs for the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260531-shikra_llcc_conf-v1-1-fa405f5a2404@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07dt-bindings: cache: qcom,llcc: Document Maili SoCJingyi Wang
Add documentation for the Last Level Cache Controller (LLCC) bindings for Qualcomm Maili SoC which is fully compatible with the one found on Qualcomm Hawi. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-maili-llcc-v2-1-dd24f05bc197@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07arm64: dts: qcom: kodiak: Move PCIe GPIOs and PHYs to root portsHongyang Zhao
The Qualcomm PCIe binding deprecates perst-gpios and wake-gpios on the host bridge and expects board reset and wake GPIOs to be described on the root port. PERST# is described there as reset-gpios. Move the PCIe PHY references in kodiak.dtsi to the PCIe0 and PCIe1 root port nodes, and move the board-specific PCIe reset and wake GPIOs in the Kodiak DTs to the corresponding root ports. Keep the PHY and GPIO resources on the same root port nodes so the Qualcomm PCIe driver can parse the root port binding instead of falling back to the legacy host bridge GPIO parsing. Signed-off-by: Hongyang Zhao <hongyang.zhao@thundersoft.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260607-rubikpi-bugfix-next-20260605-v2-1-7bf229978bcd@thundersoft.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07dt-bindings: soc: qcom,aoss-qmp: Document the Maili AOSS side channelChunkai Deng
Document the Always-on Subsystem side channel on Qualcomm Maili SoC. Signed-off-by: Chunkai Deng <chunkai.deng@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-maili-soc-binding-v2-3-21b5e9bd1aa5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07dt-bindings: sram: Document qcom,maili-imem compatibleJingyi Wang
On Qualcomm Maili platform, IMEM is a block of SRAM shared across multiple IP blocks which can fall back to "mmio-sram". Document its compatible. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-maili-soc-binding-v2-2-21b5e9bd1aa5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-08 00:31:46 +0000