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2026-07-06arm64: dts: qcom: sc8280xp: sort reserved memory regionsDmitry Baryshkov
Move memory region reserved for the GPU to its proper place in DT. Fixes: 6e9612ced0c9 ("arm64: dts: qcom: sc8280xp: create common zap-shader node") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-2-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06clk: qcom: Add support for VideoCC driver for HawiLin Li
Enable Hawi video clock driver for video SW to be able to control the clocks from the Video SW driver. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Lin Li <zhuolin.li@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702-hawi-videocc-v1-2-6c1e640b0954@oss.qualcomm.com [bjorn: Added default m, per request from Krzysztof] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06dt-bindings: clock: qcom: Add Hawi video clock controllerLin Li
Add device tree bindings for the video clock controller on Qualcomm Hawi SoC. Signed-off-by: Lin Li <zhuolin.li@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702-hawi-videocc-v1-1-6c1e640b0954@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Add EVA clock controller nodeTaniya Das
Add the device node for the EVA clock controller (evacc) for Qualcomm Glymur SoC. This clock controller provides clocks and resets to the EVA hardware block. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-4-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06Merge branch '20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com' into ↵Bjorn Andersson
arm64-for-7.3 Merge the Glymur EVA clock controller binding from topic branch, to gain access to the clock defines.
2026-07-06clk: qcom: Add EVA clock controller driver for Glymur SoCTaniya Das
Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-3-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06clk: qcom: gcc-glymur: Move EVA clocks to critical clock listTaniya Das
The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be registered as standalone GCC branch clocks. Drop these clocks from the GCC clock list and instead add their CBCR registers to the GCC critical clocks list to ensure they remain enabled during early boot. If these clocks are registered as normal branch clocks, they may be gated, which breaks access to the EVA clock controller during clock controller probe, thus leave them as critical clocks similar to other subsystem AHB and XO clocks. Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller") Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-1-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06Merge branch '20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com' into ↵Bjorn Andersson
clk-for-7.3 Merge the Glymur EVA clock controller through a topic branch, to allow the constants to also be made available in DeviceTree branches.
2026-07-06dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoCTaniya Das
Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: add CPU capacity-dmips-mhzPradyot Kumar Nayak
The Glymur SoC has two distinct core types within the same Oryon microarchitecture generation: - qcom,oryon-2-2 (cpu0-cpu5, cluster 0) - qcom,oryon-2-1 (cpu6-cpu11, cluster 1; cpu12-cpu17, cluster 2) Without capacity-dmips-mhz the Energy Aware Scheduler treats all 18 cores as equal, leading to suboptimal task placement and frequency selection. In particular, heavy tasks may be pinned to cluster 0 driving them to maximum frequency/voltage while cluster 1/2 sit idle. Fix this by using distinct capacity-dmips-mhz numbers. Values are derived from DPC (DMIPS-per-clock) measurements at the 825.6 MHz nominal operating point: oryon-2-2: 1024 (normalised baseline) oryon-2-1: 1372 (ratio ~1.34x vs oryon-2-2) Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-add-cpu-capacity-dmips-mhz-v1-1-85deced44b20@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur-crd: add Audio sound card nodeSrinivas Kandagatla
Add the sound card of Glymur-crd board with the routing for speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706064224.1328576-3-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: glymur: Add LPASS macro codecs and pinctrlSrinivas Kandagatla
Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur for proper sound support. Also add GPR (Generic Pack router) node along with APM (Audio Process Manager) and PRM (Proxy resource Manager) audio services. Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706064224.1328576-2-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: glymur-crd: Add reset GPIO to touchscreen nodePradyot Kumar Nayak
The touchscreen module on Glymur/Mahua CRDs is different from the one used on Hamoa CRDs and requires the reset-gpios to be wired to the device. Without this in place the reset line will remain permanently asserted during resume leaving the device offline and causing all I2C transactions to fail with -ENXIO. Error Logs: i2c_hid_of 3-0038: failed to change power setting. i2c_hid_of 3-0038: PM: dpm_run_callback(): i2c_hid_core_pm_resume [i2c_hid] returns -6 i2c_hid_of 3-0038: PM: failed to resume async: error -6 Add the reset GPIO so the driver can deassert the line on resume, restoring I2C communication with the device. Fixes: e6bf559f7eb9 ("arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen") Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260522-arm64-dts-glymur-crd-add-reset-gpio-to-touchscreen-v1-1-c7653924acdc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Fix gcc clock specifier for usb_mp_qmpphy nodesGopikrishna Garmidi
usb_mp_qmpphy0 and usb_mp_qmpphy1 have #clock-cells set to 0 so they take no specifier. Drop the erroneous QMP_USB43DP_USB3_PIPE_CLK argument. This fixes the following dtbs_check warning: clock-controller@100000 (qcom,glymur-gcc): clocks: [[59, 0], ..... [0]] is too long from schema $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml Fixes: 4eee57dd4df9f ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260602-glymur-fix-usb-mp-qmpphy-clock-specifier-v1-1-19c6f44d5655@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Add memory-region for audio PDVinayak Katoch
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Signed-off-by: Vinayak Katoch <vinayak.katoch@oss.qualcomm.com> Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06clk: qcom: Don't use all caps for Glymur GPUCCLuca Weiss
All other Glymur driver use "Glymur" and not all caps "GLYMUR". Align the prompt and help text. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-glymur-uncaps-v1-1-5f7065348eb2@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur-crd: Move common board nodes to shared DTSIGopikrishna Garmidi
Mahua CRD is pin-to-pin compatible with Glymur CRD, as verified against schematics; only the external peripherals connected differ. Move the common board nodes from glymur-crd.dts to glymur-crd.dtsi to enable reuse by Mahua CRD. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629-glymur-mahua-common-nodes-v3-1-98cc00943359@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06soc: qcom: ice: Support IP version beyond v3Manivannan Sadhasivam
This driver currently supports Inline Crypto Engine (ICE) IP version 3 and 4. But this driver fully supports v5 and should support upcoming versions as well. So extend the version check to support versions 3 and beyond. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260521131229.11199-1-mani@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: kaanapali: Add qcrypto node supportKuldeep Singh
Add qcrypto and cryptobam support for kaanapali target. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260514-knp_qce-v2-3-890e3372eef8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Fix unit-address mismatch for spmi_bus2Gopikrishna Garmidi
The spmi_bus2 node was named spmi@c48000, but its reg property specifies the base address as 0x0c448000. Fix the node name to spmi@c448000 to match the actual register base address. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518-glymur-fix-spmi-bus2-unit-addr-v1-1-27d6edca51e8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: hamoa: Fix clocks for HSPHYsKonrad Dybcio
The tertiary controller's HSPHY has its own toggle in TCSR, while the primary one is wired directly to the XO clock. Fix that. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518-topic-hamoa_hsphy_clk-v1-1-d85203756505@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8750: Correct DPU VBIF address space sizeKrzysztof Kozlowski
VBIF register range is 0x3000 long, so correct the code even though missing part seems without practical impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-8-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8750: Correct and complete DP address spacesKrzysztof Kozlowski
DisplayPort block on Qualcomm SM8750 has few too short address space ranges and misses four more spaces. Complete the hardware description, which in the future might be important for full feature support. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-7-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8650: Correct and complete DP address spacesKrzysztof Kozlowski
DisplayPort block on Qualcomm SM8650 has few too short address space ranges and misses four more spaces. Complete the hardware description, which in the future might be important for full feature support. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-6-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07iio: hid-sensors: Use implicit NULL pointer checksSanjay Chitroda
Replace explicit NULL pointer comparisons with implicit checks across HID sensor IIO drivers to fix kernel coding style. CHECK: Comparison to NULL could be written ... No functional change. Signed-off-by: Sanjay Chitroda <sanjayembeddedse@gmail.com> Reviewed-by: Maxwell Doose <m32285159@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-07-07iio: hid-sensors: align function parenthesis for readabilitySanjay Chitroda
Adjust alignment of parentheses across HID sensor IIO drivers to improve readability and maintain consistency with kernel coding style. While updating the formatting, group related arguments consistently in multi-line function signatures where appropriate. No functional change intended. Signed-off-by: Sanjay Chitroda <sanjayembeddedse@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-07-06fs/resctrl: Fix double-add of pseudo-locked region's RMID to free listReinette Chatre
A pseudo-locked group's RMID is freed when it is created. On unmount rmdir_all_sub() unconditionally frees all RMID of all groups, resulting in a double-free of the pseudo-locked group's RMID. The consequence of this is that the original free results in the pseudo-locked group's RMID being added to the rmid_free_lru linked list and the second free then attempts to add the same RMID entry to the rmid_free_lru again. Do not double-free a pseudo-locked group's RMID. Fixes: e0bdfe8e36f3 ("x86/intel_rdt: Support creation/removal of pseudo-locked region") Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: <stable@kernel.org> Link: https://patch.msgid.link/551432dd7e624a862b8e58314c38aaba0afff3e9.1783377598.git.reinette.chatre@intel.com
2026-07-06arm64: dts: qcom: sc8280xp: Add reg and clocks for QoS configurationXilin Wu
Add register ranges for the SC8280XP interconnect providers so the driver can program the NoC QoS registers. Move the real NoC providers under soc@0, keep clk_virt and mc_virt as virtual top-level providers, and add the clocks required for QoS programming on aggre1_noc and aggre2_noc. Signed-off-by: Xilin Wu <sophon@radxa.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-sc8280xp-qos-v1-3-15135858cd98@radxa.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add IR transmitterBiswapriyo Nath
The IR transmitting LED is connected to SPI8 controller. Reviewed-by: Sean Young <sean@mess.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-7-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add PMI632 Type-C propertyBiswapriyo Nath
The USB-C port is used for powering external devices and transfer data from/to them. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-5-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6125: Enable USB-C port handlingBiswapriyo Nath
Plug in USB-C related bits and pieces to enable USB role switching. Also, remove dr_mode to enable OTG capability. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-4-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6125-xiaomi-ginkgo: Enable vibratorBiswapriyo Nath
Enable the vibrator on the PMI632 which is used on this phone. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-3-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6125: Use 64 bit addressingBiswapriyo Nath
SM6125's SMMU uses 36bit VAs, which is a good indicator that we should increase (dma-)ranges - and by extension #address- and #size-cells to prevent things from getting lost in translation (both literally and figuratively). Do so. Fixes: 7bb7c90e0ac1 ("arm64: dts: qcom: Add Redmi Note 8T") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202603141433.MDqfoVHn-lkp@intel.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-1-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: ipq5332: Represent xo_board as fixed-factor clockLuo Jie
The xo_board clock is derived from the 48 MHz WiFi output clock (divided by 2), and not a standalone fixed frequency source. The previous implementation incorrectly modelled it as a fixed-clock with fixed frequency, which doesn't reflect the actual hardware clock tree. Update for fixed-factor-clock compatibility, and properly reference the source clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-5-f9f7e4efbd79@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06Merge tag 'mm-hotfixes-stable-2026-07-06-17-49' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Pull misc fixes from Andrew Morton: "20 hotfixes. 17 are for MM. 12 are cc:stable and the remaining 8 address post-7.1 issues or aren't considered suitable for backporting. Two patches from SJ addresses a couple of quite old DAMON issues. And two patches from Yichong Chen fixes tools/virtio build issues. The remaining patches are singletons" * tag 'mm-hotfixes-stable-2026-07-06-17-49' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: tools/include: include stdint.h for SIZE_MAX in overflow.h tools/virtio: add missing compat definitions for vhost_net_test mm: do file ownership checks with the proper mount idmap samples/damon/mtier: fail early if address range parameters are invalid mm: a second pagecache maintainer mm/damon: add a kernel-doc comment for damon_ctx->rnd_state mm/damon: add a kernel-doc comment for damon_ctx->probes mailmap: add entries for Radu Rendec selftests/mm: hmm-tests: include linux/mman.h to access MADV_COLLAPSE selftests/mm: pagemap_ioctl: use the correct page size for transact_test() fs/proc: fix KPF_KSM reported for all anonymous pages mm: page_ext: add count limit to page_ext_iter_next to prevent invalid PFN access mm/damon/ops-common: handle extreme intervals in damon_hot_score() MAINTAINERS: add Lance as an rmap reviewer mm/compaction: handle free_pages_prepare() properly in compaction_free() mm/damon/sysfs-schemes: put stats for scheme_add_dirs() internal error mm/damon/sysfs-schemes: fix dir put orders in access_pattern_add_dirs() mm: shrinker: fix NULL pointer dereference in debugfs mm: shrinker: fix shrinker_info teardown race with expansion selftests/mm: fix ksft_process_madv.sh test category
2026-07-06fs/resctrl: Fix use-after-free during unmountTony Luck
During unmount or failure teardown all mon_data structures that contain monitoring event file private data are freed after which kernfs nodes are removed. However, the RDT_DELETED flag is never set for the statically allocated default resource group. A concurrent reader of an event file associated with the default resource group may, after dropping kernfs active protection, block on rdtgroup_mutex while unmount proceeds to free the file private data and destroy the kernfs node without waiting for the reader. When the mutex is released, the reader wakes up, observes that RDT_DELETED is not set for the default group, and dereferences the already-freed file private data. The scenario can be depicted as follows: CPU0 CPU1 /* * Default resource group's * monitoring data accessible via * kernfs file with kernfs_node::priv * pointing to a struct mon_data. * User opens the file for reading. */ rdtgroup_mondata_show() /* arch encounters fatal error */ rdtgroup_kn_lock_live() resctrl_exit() atomic_inc(&rdtgroup_default.waitcount) cpus_read_lock() kernfs_break_active_protection(kn) mutex_lock(&rdtgroup_mutex) cpus_read_lock() resctrl_fs_teardown() mutex_lock(&rdtgroup_mutex) rmdir_all_sub() mon_put_kn_priv() /* Delete all mon_data structures */ rdtgroup_destroy_root() kernfs_destroy_root() rdtgroup_default.kn = NULL mutex_unlock(&rdtgroup_mutex) /* * rdtgroup_default.flags is empty so * rdtgroup_kn_lock_live() returns * &rdtgroup_default */ md = of->kn->priv; /* md points to freed mon_data */ Set RDT_DELETED for the default group unconditionally since the flag does not lead to the freeing of this statically allocated group. Do not allow a new resctrl mount if there are any waiters on default group of previous mount. A new mount will re-initialize the default group that would appear to waiters from previous mount as though the default group is accessible causing them to access the mon_data structures from the previous mount that have been removed. Fixes: 2a6566038544 ("x86/resctrl: Expand the width of domid by replacing mon_data_bits") Closes: https://sashiko.dev/#/patchset/20260508182143.14592-1-tony.luck%40intel.com?part=2 [1] Reported-by: Sashiko <sashiko-bot@kernel.org> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Chen Yu <yu.c.chen@intel.com> Cc: <stable@kernel.org> Link: https://patch.msgid.link/49a2ca3ca688f27e1a646cf90e1dc69287021127.1783377598.git.reinette.chatre@intel.com
2026-07-06arm64: dts: qcom: ipq5332: Add CMN PLL node for networking hardwareLuo Jie
Add the CMN PLL node required for networking hardware operation on IPQ5332. The CMN PLL core runs at 6 GHz on this platform, differing from others like IPQ9574. Configure the reference clock path where XO (48 MHz or 96 MHz) routes through the WiFi block's multiplier/divider to provide a stable 48 MHz reference to the CMN PLL. .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-4-f9f7e4efbd79@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06ARM: dts: qcom: pm8921: add labels for ADC channelsAntony Kurniawan Soemardi
Add label properties to all XOADC ADC channel nodes in the PM8921 PMIC device tree. This allows userspace and drivers to identify channels by name rather than relying on datasheet name. Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Antony Kurniawan Soemardi <linux@smankusors.com> Link: https://lore.kernel.org/r/20260510-pm8xxx-xoadc-label-v6-2-49700fd03005@smankusors.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sc8280xp: Move PHY, PERST, and Wake GPIOs to PCIe port nodesXilin Wu
Since describing the PCIe PHY directly under the RC node is now deprecated, move the references to the respective PCIe port nodes. And also move the PCIe PERST and wake GPIOs from the controller nodes to the corresponding PCIe port nodes on sc8280xp-based platforms: - sa8295p-adp - sa8540p-ride - sc8280xp-crd - sc8280xp-huawei-gaokun3 - sc8280xp-lenovo-thinkpad-x13s - sc8280xp-microsoft-arcata - sc8280xp-microsoft-blackrock Signed-off-by: Xilin Wu <sophon@radxa.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-8280-move-perst-wake-v1-1-5b33cef2d807@radxa.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm7325: Add Motorola Edge 30 (dubai) DTSVal Packett
The Motorola Edge 30 is a smartphone released in 2022. This commit has the following features working: - Display (simplefb) - Touchscreen - Power and volume buttons - Storage (UFS 3.1) - Battery (ADSP battmgr) - USB (Type-C, 2.0, dual-role) - Wi-Fi and Bluetooth (WCN6750 hw1.0) As there are 2 display panel options, prepare for full display support by creating a common dtsi and per-panel dts files, as is done for other upstreamed devices. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Val Packett <val@packett.cool> Link: https://lore.kernel.org/r/20260506212319.682749-2-val@packett.cool Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm7225-fairphone-fp4: Fix address in fb node nameLuca Weiss
'reg' is 0xa0000000 so the node name is missing a zero. Add it, so that the reg and address in the node name matches. No functional impact. Fixes: 4cbea668767d ("arm64: dts: qcom: sm7225: Add device tree for Fairphone 4") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260505-sm6350-misc-v1-3-0b9efc22690c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6350: Add PIL info regionLuca Weiss
Define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260505-sm6350-misc-v1-2-0b9efc22690c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6350: Add interconnects for GPU, MPSS & CDSPLuca Weiss
Add some interconnect paths for the GPU, the MPSS (modem) and CDSP. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260505-sm6350-misc-v1-1-0b9efc22690c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07Merge tag 'drm-intel-next-2026-07-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next drm/i915 feature pull for v7.3: Features and functionality: - Novalake (NVL, display versio 35) Common Mode Timing Generator (CMTG) enabling (Animesh) - NVL DC3CO enabling (Dibin) Refactoring and cleanups: - Refactor and document DP link recovery and capability tracking (Imre) - i915 and xe driver display probe/remove/suspend/resume/shutdown cleanup and unification (Jani) - Clean up bandwidth/SAGV code (Ville) - Streamline Pre/Post-CSC LUT loops (Jani) - Remove unused TGL DC3DO support (Dibin) - Make read-only array rates static const (Colin Ian King) - CDCLK sanitization improvements and cleanups (Ville) - Break i915 and xe panic dependency on struct intel_framebuffer (Jani) - GPIO pin renames and cleanups (Ville) - Unify generic irq handler error messages (Jonathan) Fixes: - Various color pipeline fixes (Chaitanya) - Fix step discontinuity in Pre/Post-CSC Gamma LUT (Sean Paul) - Improve refresh rate changes without full modeset on VRR capable eDP (Ville) - Display suspend/resume fixes (Imre) - Fix LPE audio irq for PREEMPT-RT (Maarten) - Fix HDMI scrambling enable (Jerome Tollet) - LNL bandwidth buddy programming update (Vinod) - Streamline display register wait timeouts (Ville) - Fix DP MSA VTotal (Mitul) - Fix LTPHY SSC enabling (Suraj) - Fix LOBF requirements with optimized guardband (Ankit) - Avoid full modeset for LRR vsync changes (Ankit) - Fix vtotal-vsync distance when adjusting vtotal for lower refresh rate (Ankit) - Extend VRR safe window wait for default VRR timing generator usage (Ankit) Merges: - Backmerge for v7.2-rc1 (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/934cacdbf2a37856eb5cd6337d8774b449405bd8@intel.com
2026-07-06arm64: dts: qcom: msm8953-flipkart-rimob: Enable Hall sensorCristian Cozzolino
Enable the Hall effect sensor (flip cover) for Billion Capture+. The GPIO is mapped to SW_LID events as in other qcom devices. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-6-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: msm8953-flipkart-rimob: Enable touchscreenCristian Cozzolino
This device uses a Goodix GT5688 touch controller, connected to i2c_3. Add it to the device tree. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-5-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: msm8953-flipkart-rimob: Enable WiFi/BluetoothCristian Cozzolino
Configure and enable the WCNSS which provides WiFi and Bluetooth on this device using the WCN3660B chip. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-4-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: msm8953-flipkart-rimob: Enable display and GPUCristian Cozzolino
Add the description for the display panel found on this phone. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com> Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-3-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sc8280xp-blackrock: switch to uefi rtc offsetJens Glathe
On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. On platforms where the offset is stored in a Qualcomm specific UEFI variable the variables are also accessed in a non-standard way, which means that the OS cannot assume that the variable service is available by the time the RTC driver probes. Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is stored in a UEFI variable so that the OS can determine whether to wait for it to become available. [1]: https://lore.kernel.org/r/20250423075143.11157-4-johan+linaro@kernel.org Fixes: 16a7fed11714 ("arm64: dts: qcom: sc8280xp-blackrock: dt definition for WDK2023") Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260501-blackrock-rtc-v1-1-bddf3e37fa94@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sdm850-lenovo-yoga-c630: lower PSCI cluster idleDmitry Baryshkov
With the default PSCI suspend value for cluster idle state Lenovo Yoga C630 isn't stable enough. For example it might reset if display device isn't probed early enough. Drop the bit 0x4000 from the PSCI suspend value to make C630 work in stable way. The bit was found by expertimenting with the cluster idle PSCI value. Most likely it results in the less deep sleep and more energy beign spent in the suspend state, but it's better than the non-stable system behaviour. Fixes: a1ade6cac5a2 ("arm64: dts: qcom: sdm845: Switch PSCI cpu idle states from PC to OSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260429-c630-fix-idle-v2-1-ac867dad6f21@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-13 17:24:19 +0000