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2026-07-07Merge tag 'amd-drm-next-7.3-2026-07-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-next [airlied: had to reapply drm/amdgpu: Implement "color format" DRM property by hand to amdgpu_dm_connector.c] amd-drm-next-7.3-2026-07-02: amdgpu: - Queue reset updates - Initial compute pipe reset support - Improved boundary checking for bios parsing - Cleaned up sysfs input parsing - devcoredump fixes - RAS updates and rework - VCN secure submission fixes - 8K panel fix - Add display KUnit tests - Display CRC fixes - UserQ updates - Backlight fixes - Parse panel type info from DisplayID - Align IP discovery to pci device lifetime - IOCTL boundary check fixes - Convert amdgpu_vm_lock_by_pasid() to drm_exec - Ctx fixes and cleanup - SOC15 register macro cleanups - Memory placement fixes for UVD - Disable KQ support for MI3xx - GFX9 mode2 reset fix - BO list cleanup - Soc24 aborted suspend fix - Gfx8 soft reset rework - Enable soft reset on gfx8 - Drop unnecessary BUG() and BUG_ON() in error paths - Fix power reporting unit conversion - Improve vbios command table bounds checking - UVD bounds checking improvements - VCN bounds checking improvements - PSR and replay fixes - DCN 4.2 updates - Colorop updates - DC GPIO rework - ACP fixes - Fix aperture mapping leak - Ignore_damage_clips fix - Fixes for non-4K pages - JPEG idle check fixes - Userptr fixes - GPUVM fixes - GC 11.7 updates - SMU 13 fixes amdkfd: - Initial compute pipe reset support - Allow applications to opt out of sigbus on fatal errors - Fix doorbell/mmio BO cleanup - Improved CRIU boundary checking - MQD handling rework - SMI fixes - Reset event fixes - CRIU fixes - Sysfs teardown fixes - IOCTL boundary check fixes - SVM fixes - Soft IH ring fixes - Move TBA/TMA from system to device memory radeon: - Blit fix for large BOs - r600 dpm cleanup fix drm: - Extract EDID base section header processing into helper - Parse panel type from DisplayID 2.x Display Parameters UAPI: - KFD interface for applications to select sigbus behavior on fatal errors Proposed userspace: https://github.com/ROCm/rocm-systems/pull/6190 From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260702141515.67919-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-07-07kbuild: remove srctree path from CHECK outputBen Dooks
The build does not put the full kernel path in when building outputs, so do the same when the check is run to make the output more consistent. turn the following: CC arch/riscv/lib/delay.o CHECK /home/ben/linux/arch/riscv/lib/delay.c into: CC arch/riscv/lib/delay.o CHECK arch/riscv/lib/delay.c Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Nathan Chancellor <nathan@kernel.org> Link: https://patch.msgid.link/20260622132653.446868-1-ben.dooks@codethink.co.uk [nsc: Fixed typo in subject line] Signed-off-by: Nicolas Schier <nsc@kernel.org>
2026-07-07x86/setup: do not include kexec_handover.h from asm/setup.hPratyush Yadav (Google)
x86 asm/setup.h includes linux/kexec_handover.h. This is because it is used by setup.c and kaslr.c. But this inclusion is problematic. The header is included in many places, so it results in the KHO header being propagated there. Also, the setup header is used by realmode code. If KHO header includes things like mm.h, it causes a big dump of compilation failures. Nothing in setup.h uses anything from KHO. Remove the header from setup.h, and directly include it in setup.c. which does use things from KHO. Since kaslr.c is a part of the decompressor, avoid including linux headers there directly. Instead, split out struct kho_scratch, which is the only thing the kaslr.c uses, and move it to include/asm-generic/kexec_handover.h. This should also help reduce files recompiled when kexec_handover.h changes. Signed-off-by: Pratyush Yadav (Google) <pratyush@kernel.org> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260706153751.1166003-1-pratyush@kernel.org Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-07-06accel/amdxdna: Fix VMA access raceLizhi Hou
aie2_populate_range() and amdxdna_umap_release() access a saved VMA pointer that may have already been freed, leading to a potential use-after-free. Remove the VMA accesses from these functions to avoid the race. Fixes: e486147c912f ("accel/amdxdna: Add BO import and export") Reviewed-by: Max Zhen <max.zhen@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20260609011242.2833740-1-lizhi.hou@amd.com
2026-07-06accel/amdxdna: Use unsigned long for nr_pages in amdxdna_hmm_register()Lizhi Hou
nr_pages is declared as u32 in amdxdna_hmm_register(), which may not be large enough to represent the number of pages for large mappings. Use unsigned long for nr_pages to avoid potential overflow. Fixes: ac49797c1815 ("accel/amdxdna: Add GEM buffer object management") Reviewed-by: Max Zhen <max.zhen@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20260616061532.3533469-1-lizhi.hou@amd.com
2026-07-06accel/amdxdna: Prevent PM resume deadlock in hwctx_sync_debug_bo()Lizhi Hou
amdxdna_hwctx_sync_debug_bo() invokes the hardware hwctx_sync_debug_bo() callback while holding xdna->dev_lock. The callback may call amdxdna_cmd_submit(), which in turn calls amdxdna_pm_resume_get(). If the device is suspended, amdxdna_pm_resume_get() may synchronously execute amdxdna_pm_resume(), which also acquires xdna->dev_lock, resulting in a deadlock. Avoid the deadlock by calling amdxdna_pm_resume_get() before holding xdna->dev_lock in both amdxdna_hwctx_sync_debug_bo() and amdxdna_drm_config_hwctx_ioctl() Fixes: 7ea046838021 ("accel/amdxdna: Support firmware debug buffer") Reviewed-by: Max Zhen <max.zhen@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20260616212429.3620645-1-lizhi.hou@amd.com
2026-07-07PCI: qcom: Skip PERST# GPIOs provided by downstream PCIe devicesManivannan Sadhasivam
Currently, the pcie-qcom driver recursively parses the PERST# GPIO from all child nodes defined in DT and acquires them. But this creates issues with PERST# GPIO provided by one of the child devices like the PCIe switch port. In this case, the RC driver cannot acquire the PERST# GPIO since it will be provided by the child PCIe device which was not yet enumerated during RC driver probe. Fix this by checking if the GPIO provider is a child of the RC's DT node (i.e., sits behind this PCIe controller). If so, skip it, as PERST# should be controlled by the respective PCIe client driver implementation. GPIOs provided by external GPIO controllers (e.g., TLMM in Qcom SoCs) continue to be handled normally. Fixes: 2fd60a2edb83 ("PCI: qcom: Parse PERST# from all PCIe bridge nodes") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20260616-pci-qcom-perst-fix-v1-1-27600d6ae357@oss.qualcomm.com
2026-07-07PCI: qcom: Add support for HawiMatthew Leung
Add support for the Hawi platform which has two PCIe controllers: one capable of Gen3 x2 operation and one capable of Gen4 x1 operation. Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20260625-hawi-pcie-v4-2-1a578603cd86@oss.qualcomm.com
2026-07-07dt-bindings: PCI: qcom: Document Hawi and Maili PCIe ControllersMatthew Leung
Add a dedicated schema for the PCIe controllers found on the Hawi and Maili platforms. Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> [mani: added MAINTAINERS entry and squashed the Maili patch] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260625-hawi-pcie-v4-1-1a578603cd86@oss.qualcomm.com
2026-07-07Merge tag 'drm-xe-next-2026-07-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next UAPI Changes: - Add additional error components to xe drm_ras (Riana) - Drop 'force_execlist' module parameter (Roper) Cross-subsystem Changes: - Perf events: Export perf_allow_{cpu,tracepoint} to be used by Xe (John) Display Changes: - Skip FORCE_WC and vm_bound check for external dma-bufs (Auld) Driver Changes: - Gate observation streams with perf_allow_cpu (John Hubbard) - Documentation updates and fixes (Michal, Zhan) - Remove unreleased NVL-S GuC (Daniele) - Fix pcode init path (Michal) - RTP fixes and improvements (Gustavo, Violet, Thomas, Roper) - TLB invalidation fixes and improvements (Tilak) - PXP detachment from HuC for newer platforms (Daniele) - Multi-queue fix (Niranjana) - Improve Kconfig.profile help (Rodrigo) - Xe_drm_ras and hw_error updates and fixes (Raag, Riana) - NVL-S updated PCI-IDs and W/a (Gustavo, Nitin) - Fix dma_fence refcound (Wentao) - Madvise: optimize invalidation path (Arvind) - Fix a infinite gt-reset loop in the timeout recovery (Rodrigo) - Fix wa_oob codegen recipe for external module builds (Thomas) - Avoid global forcewake in cycle query path (Xin) - Update TTM device benefical_order (Brost) - Fix buffer overflow in guc capture (Tejas) - Page-table fixes and improvements (Brian, Francois, Auld, Brost) - Removing redundant check (Lu) - General MCR and MMIO clean-up and improvements (Michal) - Don't whitelist OA registers unconditionally (Ashutosh) - SVM error return fix (Brost) - Userptr fix and small related clean-ups (Shuicheng) - Don't attempt to process FAST_REQ or EVENT relays on PF (Michal) - Couple fdinfo improvements (Auld) - Drop manual VF check on i2c (Raag) - Probe info outside of xe_info_init functions (Gustavo) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/akf7xr96MI4Rd6Qj@intel.com
2026-07-06x86/cpu: Hide and rename static_cpu_has()Borislav Petkov (AMD)
cpu_feature_enabled() is the one to use to test feature flags so hide the static thing which doesn't pay attention to disabled mask bits anyway. Use the following command to do the replacement: $ git grep --files-with-matches -w static_cpu_has -- ':(exclude)*cpufeature.h' \ | xargs sed -i 's/static_cpu_has(/cpu_feature_enabled\(/g' There should be no functional changes resulting from this. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Link: https://patch.msgid.link/20260620015041.336288-1-bp@kernel.org
2026-07-07fpga: dfl: fme: add error handlingGriffin Kroah-Hartman
Add error handling to devm_kasprint in fme_perf_pmu_register(). Assisted-by: gkh_clanker_2000 Fixes: 724142f8c42a ("fpga: dfl: fme: add performance reporting support") Cc: stable@kernel.org Cc: Xu Yilun <yilun.xu@intel.com> Cc: Tom Rix <trix@redhat.com> Cc: Moritz Fischer <mdf@kernel.org> Signed-off-by: Griffin Kroah-Hartman <griffin@kroah.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [ Yilun: Fix stable tag, add Fixes tag ] Reviewed-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/2026070620-unwired-clay-f6cc@gregkh Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
2026-07-06bus: qcom-ebi2: Fix clock leak on probe failureRuoyu Wang
qcom_ebi2_probe() enables the EBI2X and EBI2 clocks before it walks child nodes and populates child devices. If reading a child node's reg property fails, or if of_platform_default_populate() fails, probe returns without disabling either clock. Route those failure paths through the existing clock cleanup labels so a failed probe does not leave the clocks prepared and enabled. Fixes: 335a12754808 ("bus: qcom: add EBI2 driver") Signed-off-by: Ruoyu Wang <ruoyuw560@gmail.com> Link: https://lore.kernel.org/r/20260620080406.1970447-1-ruoyuw560@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06Revert "clk: qcom: regmap-phy-mux: Rework the implementation"Konrad Dybcio
This reverts commit e108373c54fbc844b7f541c6fd7ecb31772afd3c. This has been reported to break PCIe on at least SM8350 and Eliza platforms. I had originally tested this on Hamoa (X1E) where there were no adverse effects. It's highly likely that this stems from a difference in how the bootloader configures the clocks. Revert the offending change to fix the issue in the immediate, with the intent to revisit it in the upcoming cycle. Reported-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reported-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Fixes: e108373c54fb ("clk: qcom: regmap-phy-mux: Rework the implementation") Closes: https://lore.kernel.org/all/c675lcfptr4xgg4hcjp66unmuozgsvgwvtymh7on6jcipjrdw7@jy4h7fkwqwjg/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260622-topic-phymux_revert-v1-1-f6ec85523840@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06soc: qcom: qcom_stats: Add SoCCP and DCP subsystems statsSneh Mankad
Add SMEM items for SoC Control Processor and Display Co-Processor subsystem stats which are present in Hawi SoC. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260615-add_subsystem_lpm_stats-v1-1-d40fc7c755da@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07fpga: stratix10-soc: Fix SVC mailbox handling during reconfigurationTien Sung Ang
Fix incorrect stratix10_svc_done() usage during FPGA reconfiguration. Do not call stratix10_svc_done() at the end of write_init() on success, so the SVC session remains active through write() and write_complete(). Call stratix10_svc_done() on failure in write_init() and write() so the shared SVC mailbox is released when reconfiguration aborts, allowing coexistence with other SVC clients such as soc64-hwmon. Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver") Cc: stable@vger.kernel.org # 5.1+ Signed-off-by: Tien Sung Ang <tien.sung.ang@altera.com> Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/8768ce3260489c9febdfce08e27d03f5f5ed9c33.1782801986.git.tze.yee.ng@altera.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
2026-07-07fpga: xilinx-pr-decoupler: Use devm_clk_get_prepared()Michal Simek
The driver keeps the "aclk" clock prepared but disabled in its idle state, toggling only the atomic clk_enable()/clk_disable() around register accesses in the bridge enable_set/enable_show callbacks. At probe time this was open-coded as clk_prepare_enable() immediately followed by clk_disable(), leaving the clock prepared, with a matching clk_unprepare() in the error path and in remove(). devm_clk_get_prepared() expresses exactly this: it gets and prepares the clock and unprepares it automatically on driver detach. Use it to drop the manual prepare/disable dance, the error-path unprepare, and the now-empty clock teardown in remove(). Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/8ca8ee5ba720b608a41f842d2b743302e5500ad0.1782205286.git.michal.simek@amd.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
2026-07-06arm64: dts: qcom: sm8350-hdk: enable Iris coreDmitry Baryshkov
Enable video en/decoder on the SM8350 HDK board. The firmware is not (yet) a part of linux-firmware and needs to be extracted from Android data. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-6-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8350: add Iris deviceDmitry Baryshkov
Add Iris and video clock controller devices, describing the Iris2 core present on this platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-5-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sc8280xp-x13s: Enable IrisKonrad Dybcio
Enable Iris and point the driver to the correct firmware file. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-4-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sc8280xp: Add Iris coreKonrad Dybcio
Add the required nodes to enable Iris core on SC8280XP. [ bod: added interconnect tags ] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [ johan: use sm8350 videocc defines ] Signed-off-by: Johan Hovold <johan+linaro@kernel.org> [ bod: dropped video encoder/decoder declarations ] Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> [ db: dropped llcc icc, switched to sc8280xp compat, corrected OPP table ] Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-3-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sc8280xp: sort reserved memory regionsDmitry Baryshkov
Move memory region reserved for the GPU to its proper place in DT. Fixes: 6e9612ced0c9 ("arm64: dts: qcom: sc8280xp: create common zap-shader node") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-2-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06clk: qcom: Add support for VideoCC driver for HawiLin Li
Enable Hawi video clock driver for video SW to be able to control the clocks from the Video SW driver. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Lin Li <zhuolin.li@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702-hawi-videocc-v1-2-6c1e640b0954@oss.qualcomm.com [bjorn: Added default m, per request from Krzysztof] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06dt-bindings: clock: qcom: Add Hawi video clock controllerLin Li
Add device tree bindings for the video clock controller on Qualcomm Hawi SoC. Signed-off-by: Lin Li <zhuolin.li@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702-hawi-videocc-v1-1-6c1e640b0954@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Add EVA clock controller nodeTaniya Das
Add the device node for the EVA clock controller (evacc) for Qualcomm Glymur SoC. This clock controller provides clocks and resets to the EVA hardware block. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-4-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06Merge branch '20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com' into ↵Bjorn Andersson
arm64-for-7.3 Merge the Glymur EVA clock controller binding from topic branch, to gain access to the clock defines.
2026-07-06clk: qcom: Add EVA clock controller driver for Glymur SoCTaniya Das
Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-3-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06clk: qcom: gcc-glymur: Move EVA clocks to critical clock listTaniya Das
The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be registered as standalone GCC branch clocks. Drop these clocks from the GCC clock list and instead add their CBCR registers to the GCC critical clocks list to ensure they remain enabled during early boot. If these clocks are registered as normal branch clocks, they may be gated, which breaks access to the EVA clock controller during clock controller probe, thus leave them as critical clocks similar to other subsystem AHB and XO clocks. Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller") Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-1-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06Merge branch '20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com' into ↵Bjorn Andersson
clk-for-7.3 Merge the Glymur EVA clock controller through a topic branch, to allow the constants to also be made available in DeviceTree branches.
2026-07-06dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoCTaniya Das
Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: add CPU capacity-dmips-mhzPradyot Kumar Nayak
The Glymur SoC has two distinct core types within the same Oryon microarchitecture generation: - qcom,oryon-2-2 (cpu0-cpu5, cluster 0) - qcom,oryon-2-1 (cpu6-cpu11, cluster 1; cpu12-cpu17, cluster 2) Without capacity-dmips-mhz the Energy Aware Scheduler treats all 18 cores as equal, leading to suboptimal task placement and frequency selection. In particular, heavy tasks may be pinned to cluster 0 driving them to maximum frequency/voltage while cluster 1/2 sit idle. Fix this by using distinct capacity-dmips-mhz numbers. Values are derived from DPC (DMIPS-per-clock) measurements at the 825.6 MHz nominal operating point: oryon-2-2: 1024 (normalised baseline) oryon-2-1: 1372 (ratio ~1.34x vs oryon-2-2) Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-add-cpu-capacity-dmips-mhz-v1-1-85deced44b20@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur-crd: add Audio sound card nodeSrinivas Kandagatla
Add the sound card of Glymur-crd board with the routing for speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706064224.1328576-3-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: glymur: Add LPASS macro codecs and pinctrlSrinivas Kandagatla
Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur for proper sound support. Also add GPR (Generic Pack router) node along with APM (Audio Process Manager) and PRM (Proxy resource Manager) audio services. Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706064224.1328576-2-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: glymur-crd: Add reset GPIO to touchscreen nodePradyot Kumar Nayak
The touchscreen module on Glymur/Mahua CRDs is different from the one used on Hamoa CRDs and requires the reset-gpios to be wired to the device. Without this in place the reset line will remain permanently asserted during resume leaving the device offline and causing all I2C transactions to fail with -ENXIO. Error Logs: i2c_hid_of 3-0038: failed to change power setting. i2c_hid_of 3-0038: PM: dpm_run_callback(): i2c_hid_core_pm_resume [i2c_hid] returns -6 i2c_hid_of 3-0038: PM: failed to resume async: error -6 Add the reset GPIO so the driver can deassert the line on resume, restoring I2C communication with the device. Fixes: e6bf559f7eb9 ("arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen") Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260522-arm64-dts-glymur-crd-add-reset-gpio-to-touchscreen-v1-1-c7653924acdc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Fix gcc clock specifier for usb_mp_qmpphy nodesGopikrishna Garmidi
usb_mp_qmpphy0 and usb_mp_qmpphy1 have #clock-cells set to 0 so they take no specifier. Drop the erroneous QMP_USB43DP_USB3_PIPE_CLK argument. This fixes the following dtbs_check warning: clock-controller@100000 (qcom,glymur-gcc): clocks: [[59, 0], ..... [0]] is too long from schema $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml Fixes: 4eee57dd4df9f ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260602-glymur-fix-usb-mp-qmpphy-clock-specifier-v1-1-19c6f44d5655@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Add memory-region for audio PDVinayak Katoch
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Signed-off-by: Vinayak Katoch <vinayak.katoch@oss.qualcomm.com> Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06clk: qcom: Don't use all caps for Glymur GPUCCLuca Weiss
All other Glymur driver use "Glymur" and not all caps "GLYMUR". Align the prompt and help text. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-glymur-uncaps-v1-1-5f7065348eb2@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur-crd: Move common board nodes to shared DTSIGopikrishna Garmidi
Mahua CRD is pin-to-pin compatible with Glymur CRD, as verified against schematics; only the external peripherals connected differ. Move the common board nodes from glymur-crd.dts to glymur-crd.dtsi to enable reuse by Mahua CRD. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629-glymur-mahua-common-nodes-v3-1-98cc00943359@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06soc: qcom: ice: Support IP version beyond v3Manivannan Sadhasivam
This driver currently supports Inline Crypto Engine (ICE) IP version 3 and 4. But this driver fully supports v5 and should support upcoming versions as well. So extend the version check to support versions 3 and beyond. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260521131229.11199-1-mani@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: kaanapali: Add qcrypto node supportKuldeep Singh
Add qcrypto and cryptobam support for kaanapali target. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260514-knp_qce-v2-3-890e3372eef8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: glymur: Fix unit-address mismatch for spmi_bus2Gopikrishna Garmidi
The spmi_bus2 node was named spmi@c48000, but its reg property specifies the base address as 0x0c448000. Fix the node name to spmi@c448000 to match the actual register base address. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518-glymur-fix-spmi-bus2-unit-addr-v1-1-27d6edca51e8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: hamoa: Fix clocks for HSPHYsKonrad Dybcio
The tertiary controller's HSPHY has its own toggle in TCSR, while the primary one is wired directly to the XO clock. Fix that. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518-topic-hamoa_hsphy_clk-v1-1-d85203756505@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8750: Correct DPU VBIF address space sizeKrzysztof Kozlowski
VBIF register range is 0x3000 long, so correct the code even though missing part seems without practical impact. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-8-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8750: Correct and complete DP address spacesKrzysztof Kozlowski
DisplayPort block on Qualcomm SM8750 has few too short address space ranges and misses four more spaces. Complete the hardware description, which in the future might be important for full feature support. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-7-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm8650: Correct and complete DP address spacesKrzysztof Kozlowski
DisplayPort block on Qualcomm SM8650 has few too short address space ranges and misses four more spaces. Complete the hardware description, which in the future might be important for full feature support. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-6-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-07iio: hid-sensors: Use implicit NULL pointer checksSanjay Chitroda
Replace explicit NULL pointer comparisons with implicit checks across HID sensor IIO drivers to fix kernel coding style. CHECK: Comparison to NULL could be written ... No functional change. Signed-off-by: Sanjay Chitroda <sanjayembeddedse@gmail.com> Reviewed-by: Maxwell Doose <m32285159@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-07-07iio: hid-sensors: align function parenthesis for readabilitySanjay Chitroda
Adjust alignment of parentheses across HID sensor IIO drivers to improve readability and maintain consistency with kernel coding style. While updating the formatting, group related arguments consistently in multi-line function signatures where appropriate. No functional change intended. Signed-off-by: Sanjay Chitroda <sanjayembeddedse@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-07-06fs/resctrl: Fix double-add of pseudo-locked region's RMID to free listReinette Chatre
A pseudo-locked group's RMID is freed when it is created. On unmount rmdir_all_sub() unconditionally frees all RMID of all groups, resulting in a double-free of the pseudo-locked group's RMID. The consequence of this is that the original free results in the pseudo-locked group's RMID being added to the rmid_free_lru linked list and the second free then attempts to add the same RMID entry to the rmid_free_lru again. Do not double-free a pseudo-locked group's RMID. Fixes: e0bdfe8e36f3 ("x86/intel_rdt: Support creation/removal of pseudo-locked region") Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: <stable@kernel.org> Link: https://patch.msgid.link/551432dd7e624a862b8e58314c38aaba0afff3e9.1783377598.git.reinette.chatre@intel.com
2026-07-06arm64: dts: qcom: sc8280xp: Add reg and clocks for QoS configurationXilin Wu
Add register ranges for the SC8280XP interconnect providers so the driver can program the NoC QoS registers. Move the real NoC providers under soc@0, keep clk_virt and mc_virt as virtual top-level providers, and add the clocks required for QoS programming on aggre1_noc and aggre2_noc. Signed-off-by: Xilin Wu <sophon@radxa.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-sc8280xp-qos-v1-3-15135858cd98@radxa.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add IR transmitterBiswapriyo Nath
The IR transmitting LED is connected to SPI8 controller. Reviewed-by: Sean Young <sean@mess.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-7-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-14 09:23:48 +0000