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2026-08-06dt-bindings: mfd: qcom,tcsr: Document the IPQ9650 TCSR blockKathiravan Thirumoorthy
Document the TCSR block found on the Qualcomm's IPQ9650 SoC. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260727-ipq9650_tcsr_binding-v1-1-931ac0e056d0@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: leds: lacie,ns2-leds: Convert to DT schemaNinad Naik
Convert lacie,ns2-leds to DT schema. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ninad Naik <ninadnaik07@gmail.com> Closes: https://lore.kernel.org/r/202607231542.6ovJrInT-lkp@intel.com/ Link: https://patch.msgid.link/20260728183945.12008-1-ninadnaik07@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: leds: nxp,pca963x: Add multicolor LED supportLoic Poulain
Add support for grouping individual PCA963x channels into a multicolor LED by introducing a multi-led@N node pattern. This follows the convention established by other multicolor LED drivers such as kinetic,ktd202x. This is necessary to support and model hardware setups where multiple PWM channels drive a single physical RGB LED. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://patch.msgid.link/20260727-monza-leds-v8-2-6e7e93d44dba@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: leds: nxp,pca963x: Fix reg maximum for pca9635Loic Poulain
The pca9635 supports 16 LED channels, unlike the pca9634 which only supports 8. The allOf conditional grouped both chips under a single else branch capping reg at a maximum of 7. Give pca9634 its own if/then block and set maximum: 15 unconditionally in the top-level led@ node, making it the default for pca9635 and any future compatible. Also tighten the node name regex from [0-9a-f]+ to [0-9a-f] to match the single-digit hardware limit. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://patch.msgid.link/20260727-monza-leds-v8-1-6e7e93d44dba@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: leds: backlight: Convert TPS65217 to DT schemaEduard Bostina
Convert the Texas Instruments TPS65217 bindings to DT schema. During the conversion, the following updates were made: - Documented the 'regulators', 'charger' and 'pwrbutton' child nodes, which are used by the boards but were missing from the old txt binding. - Documented the 'interrupts', 'interrupt-controller', '#interrupt-cells' and 'ti,pmic-shutdown-controller' properties, which are used by the am335x boards and read by the driver. The regulator/tps65217.txt binding documented the same 'ti,tps65217' compatible and is superseded by this schema, so remove it as well. Signed-off-by: Eduard Bostina <egbostina@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260723100605.628882-5-egbostina@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06dt-bindings: mfd: qcom,spmi-pmic: Document haptics deviceFenglin Wu
Some of the Qualcomm SPMI PMIC has haptics device in it, add it in the device list. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-qcom-spmi-haptics-v5-2-77128ebbdd2d@oss.qualcomm.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-08-06spi: dt-bindings: snps,dw-apb-ssi: Document Axiado AX3005Swark Yang
The Axiado AX3005 SPI controller is software-compatible with the Synopsys DesignWare APB SSI 1.01a programming interface. Document the "axiado,ax3005-spi" SoC-specific compatible with "snps,dwc-ssi-1.01a" as its fallback. This preserves identification of the AX3005 integration while allowing the controller to use the existing DesignWare APB SSI support. Signed-off-by: Swark Yang <syang@axiado.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260805-upstrea-ax3005-spi-v4-v4-1-5b8bc11cb841@axiado.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-06ASoC: dt-bindings: cirrus,cs42l43: Add CS42L44 variantCharles Keepax
The cs42l44 is a cost optimised variant of cs42l43b. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://patch.msgid.link/20260805131942.45729-1-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-06dt-bindings: arm-smmu: qcom: add compatible for IPQ9650 SoCKathiravan Thirumoorthy
Add the compatible string for the APPS SMMU present on the Qualcomm IPQ9650 SoC. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-08-06Merge tag 'w1-drv-7.3' of ↵Greg Kroah-Hartman
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next Krzysztof writes: 1-Wire bus drivers for v7.3 1. Improve (fix) ds2482 driver module autoloading, when probing from Devicetree. 2. Convert HDQ One Wire devicetree bindings to DT schema format. 3. Fixes for handling incorrect data from potentially malicious hardware, looking theoretical issues but still worth to fix. Affected drivers: w1 core code, ds28e17 and ds2482. * tag 'w1-drv-7.3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1: w1: ds2482: Fix signedness bug in ds2482_w1_triplet() w1: validate slave string length before checking separator w1: ds28e17: reject an oversize length on an I2C block read dt-bindings: w1: Convert HDQ One Wire to DT schema w1: ds2482: add OF device match table
2026-08-05dt-bindings: dpll: zl3073x: ZL30643 is compatibleVincent Jardin
The Microchip ZL30643 (chip ID 0x0E3B) is a member of the ZL3064x line card timing family. It is register compatible with the 3-channel ZL30733 (chip ID 0x0E95) of the ZL3073x family: both datasheets describe the same register map and use the same chip-ID encoding. Describe it with a fallback to microchip,zl30733 rather than a new standalone compatible. Signed-off-by: Vincent Jardin <vjardin@free.fr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260730-for-upstream-zl30643-v2-1-0ea0bbd03755@free.fr Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-08-06Merge tag 'mediatek-drm-next-20260731' of ↵Dave Airlie
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next - 20260731 1. cec: Correct the compatibles for mt7623-mt8167 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patch.msgid.link/20260730233317.3222-1-chunkuang.hu@kernel.org
2026-08-05dt-bindings: clock: rockchip: Add RV1106 CRU supportSimon Glass
Add the clock binding header and schema for the Rockchip RV1106 clock and reset unit. The clock IDs are numbered continuously from 0, in the same way as the RV1103B. The header also covers the MMC drive and sample phase clocks, which the CRU provides using control registers in the GRF region. The RV1103 is a package variant of the RV1106 and uses the same CRU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260729133609.3465563-2-sjg@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-08-05Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3Geert Uytterhoeven
Renesas R-Car X5H CPG DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Clock Pulse Generator (CPG), shared by driver and DT source files.
2026-08-05dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse GeneratorGeert Uytterhoeven
Document support for the Renesas R-Car X5H Clock Pulse Generator, and add binding definitions for a limited initial set of clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/7a33c99816c850faeec5c17532811faf78959a1d.1785941595.git.geert+renesas@glider.be
2026-08-05dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoderBiju Das
Document the LVDS encoder IP found on the RZ/G3L SoC. It supports single-link mode. LVDS and the DSI interface share a peripheral clock and the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be used at the same time as MIPI-DSI. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260729125516.230757-10-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2026-08-05dt-bindings: display: renesas,rzg2l-du: Document RZ/G3L SoCBiju Das
The DU block on the RZ/G3L SoC is identical to the one found on the RZ/G2L SoC. However, it supports the DSI, DPI, and LVDS interfaces, while the RZ/G2L supports only the DSI and DPI interfaces. Due to this difference, a SoC-specific compatible string, 'renesas,r9a08g046-du', is added for the RZ/G3L SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260729125516.230757-8-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2026-08-05dt-bindings: display: bridge: renesas,dsi: Document RZ/G3LBiju Das
The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY timings and also the PLLCLK is ungateble clock. Add the compatible string "renesas,r9a08g046-mipi-dsi" to handle these difference for the Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260729125516.230757-2-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2026-08-05dt-bindings: iio: dac: add support for mcp47a1Joshua Crofts
The Microchip MCP47A1 is a 6-bit volatile Digital-to-Analog converter which communicates via I2C. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Joshua Crofts <joshua.crofts1@gmail.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
2026-08-05iio: Update email for Maxwell DooseMaxwell Doose
I'm transitioning to a new email, add mapping and update MAINTAINERS entries to keep email up to date. Signed-off-by: Maxwell Doose <maxwell@maxwelld.cc> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
2026-08-05dt-bindings: iio: flow: add Sensirion SLF3S liquid flow sensorWadim Mueller
Document the bindings for the Sensirion SLF3S family of digital liquid-flow sensors on I2C. The family currently covers the SLF3S-0600F, SLF3S-1300F and SLF3S-4000B variants. All variants share the same register map and differ only in the flow scale factor and the calibrated measurement range, which the driver reads back from the product-information register. Since that lookup is needed in any case, a fallback compatible would buy nothing, so each variant gets its own compatible without a fallback. A future drop-in compatible part can then claim one of these compatibles and work on kernels that do not know its product ID yet. The active calibration medium (water / IPA) is runtime-switchable via the in_volumeflow_medium sysfs attribute and therefore not a DT property. Signed-off-by: Wadim Mueller <wafgo01@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
2026-08-04Merge tag 'qcom-drivers-for-7.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.3 Add Maili platform bindings for SCM, IMEM, AOSS, and PMIC GLINK. Add Shikra IMEM, RPM SMD, LLCC, and UBWC support, including handling for firmware-configured LLCC ECC interrupts. Add the generic Peripheral Authentication Service with SCM and OP-TEE backends, and migrate the MSM DRM and IPA drivers to it. Add SCM SMC-call tracepoints and configurable minidump delivery through always-on SRAM. Correct SCM download-mode pointer ordering and improve download-mode probe diagnostics. Rework the UBWC configuration database and add Milos and Shikra configuration. Add protection-domain mappings for SA8775P and QCS8300, support newer ICE versions, Hawi subsystem statistics, and SDM850 identification. Simplify Qualcomm SoC Kconfig selection and architecture dependencies. Use managed resources in EBI2 and RPMh RSC probe paths to correct cleanup on failures. * tag 'qcom-drivers-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (44 commits) soc: qcom: llcc: Skip ECC interrupt setup on Shikra, pre-configured by DSF dt-bindings: sram: Document qcom,shikra-imem compatible net: ipa: Switch to generic PAS TZ APIs firmware: qcom: scm: Add minidump SRAM support firmware: qcom: scm: use dev_err_probe() for dload address failure firmware: qcom: scm: Fix missing smp_load_acquire() dt-bindings: firmware: qcom,scm: Add minidump SRAM property drm/msm: Switch to generic PAS TZ APIs bus: qcom-ebi2: use managed resources for clocks and children soc: qcom: rpmh-rsc: manage PM notifiers with devres firmware: qcom: scm: Allow QSEECOM on Honor Magicbook Art 14 firmware: qcom: scm: instrument SMC call path with tracepoints firmware: qcom: scm: add trace events for the SMC call interface soc: qcom: Avoid SCM and SPM for cpuidle drivers soc: qcom: Make important drivers default soc: qcom: Restrict drivers per ARM/ARM64 soc: qcom: Hide all drivers behind selectable menu MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service firmware: qcom: Add a PAS TEE service firmware: qcom_scm: Migrate to generic PAS service ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-08-04Merge tag 'amlogic-drivers-for-v7.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers Amlogic drivers for v7.3: - Clock measure debugfs fixup - Clock measure support for Amlogic A1 & T7 * tag 'amlogic-drivers-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: soc: amlogic: meson-clk-measure: remove debugfs tree soc: amlogic: clk-measure: Add A1 and T7 support dt-bindings: soc: amlogic: clk-measure: Add A1 and T7 compatible Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-08-04spi: Few cleanups while looking at num-csMark Brown
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> says: Few minor cleanups for DT bindings and Andes driver. Patches do not have inter-dependencies. Link: https://patch.msgid.link/20260804-spi-num-cs-v1-0-4ccb13dcc7b0@oss.qualcomm.com
2026-08-04spi: dt-bindings: spi-cadence: Drop duplicated type/refKrzysztof Kozlowski
spi-controller.yaml schema already defines this $ref for this property, so binding does not have to. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-4-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: dt-bindings: axiado,ax3000-spi: Drop duplicated type/refKrzysztof Kozlowski
spi-controller.yaml schema already defines this $ref for this property, so binding does not have to. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-3-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: dt-bindings: marvell,armada-3700-spi: Drop redundant num-csKrzysztof Kozlowski
'num-cs' property is a single integer, thus the binding should not set maxItems. This could be replaced with proper min/max constraints for values, except that such constraints are not known. spi-controller.yaml schema already defines this property, so its presence here is redundant. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-2-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: dt-bindings: andestech,ae350-spi: Drop redundant num-csKrzysztof Kozlowski
'num-cs' property is a single integer, thus the binding should not set maxItems. This could be replaced with proper min/max constraints for values, except that hardware (as expressed in driver) supports only one native chipselect, thus constraint of "const:1" would make the property implied by the compatible. spi-controller.yaml schema already defines this property, so its presence here is redundant. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-1-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04ASoC: qcom: add AudioReach TDM backend supportMark Brown
Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> says: Add AudioReach support for LPASS Audio IF based TDM backends and wire it up for the sc8280xp machine driver. The series first adds topology-driven Audio IF source/sink handling so the DSP interface parameters can be described by topology while runtime media format and slot configuration still come from the machine driver. It then adds TDM DAI operations for q6apm-lpass-dais, exposes the Audio IF clock IDs through the q6dsp-lpass-ports binding and q6prm clock tables, and introduces common QCOM helpers for parsing standard dai-tdm-slot-* properties from backend CPU and codec endpoints. Finally, sc8280xp uses the common helpers during hw_params to program CPU and codec TDM slots, derive the backend bit clock from the active PCM parameters, and request the CPU and codec clocks before the stream is started. Link: https://patch.msgid.link/20260804070307.117119-1-prasad.kumpatla@oss.qualcomm.com
2026-08-04dt-bindings: sound: qcom,sm8250: allow TDM slot propertiesPrasad Kumpatla
Allow standard dai-tdm-slot-* properties in the CPU and codec child nodes of a DAI link. The QCOM machine driver parses these child nodes to configure TDM slots on the active CPU and codec DAIs. The properties are already defined by the common tdm-slot binding, but qcom,sm8250.yaml currently rejects them because the CPU and codec child nodes set additionalProperties: false. Permit dai-tdm-slot-num, dai-tdm-slot-width and dai-tdm-slot-[rt]x-mask there so boards using TDM backends can describe the slot layout without schema warnings. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260804070307.117119-6-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04ASoC: SOF: ipc4-topology: Pipeline params improvementsMark Brown
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> says: Improve handling of some corner cases that are not used by current topology designs, but can be crafted within the rules of a topology file. For example branching topologies, where a single input routed to multiple output endpoints. The already configured part of the graph places constraint on how the new branch can be configured. Handling of process modules also updated to be able to 'guess' what parameters can be changed by the module and allow flexible operation. Link: https://patch.msgid.link/20260730121729.18673-1-peter.ujfalusi@linux.intel.com
2026-08-04dt-bindings: remoteproc: qcom,nord-pas: Document Nord PASShawn Guo
Add a dedicated binding for the Qualcomm Nord SoC PAS devices: ADSP and CDSPs. Nord ADSP uses CX and MX power domains while the CDSPs add an NSP domain on top of that. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-08-04dt-bindings: net: Correct white-space styleKrzysztof Kozlowski
Correct a few white-space issues, like double space after '=' or before bracket '{' characters, which will be flagged by dt-check-style. No functional changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260801195505.235099-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2026-08-04dt-bindings: power: Add Amlogic A9 power domainsXianwei Zhao
Add devicetree binding document and related header file for Amlogic A9 secure power domains. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-08-04spi: Add support for StarFive JHB100 SFCMark Brown
Changhuang Liang <changhuang.liang@starfivetech.com> says: This serial add support for the StarFive JHB100 SoC SPI Flash Controller (SFC), which is based on the Synopsys DesignWare SSI version 2.00a but with some customizations and it also add enhanced SPI for DesignWare SPI controllers. I picked up some patches from series [1]. This series depends on the series [2]: [1] https://lore.kernel.org/all/20221212180732.79167-1-sudip.mukherjee@sifive.com/ [2] https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@starfivetech.com/ v1: https://lore.kernel.org/all/20260709055204.138168-1-changhuang.liang@starfivetech.com/ Link: https://patch.msgid.link/20260803124044.156998-1-changhuang.liang@starfivetech.com
2026-08-04spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-sfcChanghuang Liang
Add a new compatible string "starfive,jhb100-sfc" for the StarFive JHB100 SPI Flash Controller, it based on the Synopsys DesignWare SSI version 2.00a but with minor modifications. Due to these minor modifications, it only supports access for flash memory and requires a system controller register to configure the address mode filter for SPI NOR flash devices. The starfive,sfc-filter-syscon property is required to provide a phandle to the system controller that manages switching between 3-byte and 4-byte addressing modes, essential for supporting SPI NOR flash devices with different address width requirements. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260803124044.156998-11-changhuang.liang@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04dt-bindings: mmc: sunxi: add compatible string for Allwinner A733 MMC0/1/2Jerome Brunet
The A733 MMC0/1/2 controllers are compatible with the D1 ones. Add an A733-specific compatible string, with the D1 as fallback. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-08-04dt-bindings: mmc: Document fixed-layout NVMEM provider supportLoic Poulain
Allow an eMMC hardware partition node to describe an NVMEM layout so the partition can be exposed as an NVMEM provider. This lets a partition (e.g. an eMMC boot partition) store device-specific information such as a WiFi MAC address or a Bluetooth BD address and reference it through NVMEM cells. Accept "fixed-layout" as the partition node compatible, in addition to "fixed-partitions", so the layout can be described directly on the partition node. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-08-04dt-bindings: soc: sophgo: add Milk-V Duo 256M boardChen-Yu Yeh
Add compatible string for the Milk-V Duo 256M board. Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260725175346.139173-2-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <chen.wang@linux.dev>
2026-08-03regulator: dt-bindings: ti,pbias-omap: Convert to DT schemaBhargav Joshi
Convert Texas Instruments PBIAS internal regulator from text to DT schema. Since all in tree DT uses SoC specific compatible along with "ti,pbias-omap" Convert compatible property to require the two-string form. Add child regulator nodes as property as they are fixed and node name is matched by driver. Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260729-ti-pbias-omap-v3-1-20fcc0bdc890@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-03dt-bindings: iio: adc: Add ltc2378Marcelo Schmitt
Document how to describe LTC2378-20 and similar ADCs in device tree. Reviewed-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
2026-08-03dt-bindings: iio: imu: icm42600: Add icm42607Chris Morgan
Add the ICM42607 and ICM42607P inertial measurement unit. This device is functionally very similar to the icm42600 series with a very different register layout. The icm42607 currently does not use an interrupt because wake on movement and buffers are not supported, and cannot be implemented on my test device which lacks an interrupt line. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
2026-08-03dt-bindings: iio: imu: icm42600: Add mount-matrixChris Morgan
Add mount-matrix attribute to schema. This attribute has been supported since the first revision of this driver, but was not documented. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
2026-08-03dt-bindings: serial: 8250: Add Aspeed AST2600 and AST2700 uart compatibleYu-Che Hsieh
The AST2600 and AST2700 VUART controllers are identical to the AST2500 VUART controller. Add the "aspeed,ast2600-vuart" and "aspeed,ast2700-vuart" compatible strings and fall back to "aspeed,ast2500-vuart" for compatibility with the existing driver. Signed-off-by: Yu-Che Hsieh <yc_hsieh@aspeedtech.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260721-upstream-ast2700-vuart-support-v1-1-b4ed612b1aa2@aspeedtech.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-08-03regulator: dt-bindings: Correct white-space styleKrzysztof Kozlowski
Correct a few white-space issues, like double space after '=' character, which will be flagged by dt-check-style. No functional changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260801195440.234183-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-03spi: dt-bindings: nuvoton,ma35d1-qspi: Disallow GPIO chip selectsChi-Wen Weng
The generic SPI controller binding allows GPIO-based chip selects, but the MA35D1 QSPI driver currently supports only the controller's native chip selects. Disallow the cs-gpios property so that the binding matches the functionality provided by the driver. Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com> Link: https://patch.msgid.link/20260803024048.1641756-1-cwweng.linux@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-03ASoC: dt-bindings: Correct white-space styleKrzysztof Kozlowski
Correct a few white-space issues, like double space after '=' character, which will be flagged by dt-check-style. No functional changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260801195425.234120-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-03dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIOPaul Louvel
Some QE GPIO pins have an associated interrupt line in the QE PIC to signal state changes on the pin. Add the corresponding interrupt-controller / nexus properties to the QE GPIO binding. Because the GPIO controller does not perform any interrupt handling itself, a nexus node (interrupt-map) is used to map each GPIO line supporting IRQ to the parent QE PIC interrupt domain. As the QE PIC can be configured to generate an interrupt on either a high-to-low transition or any change in signal state, three interrupt-map entries are needed per GPIO pin that can yield an interrupt (falling, both, and the "none" case which defaults to both in QE PIC). This overhead is necessary because the interrupt-map-pass-thru property is not part of the DT specification. The interrupt-map property is optional: it is not required for GPIO banks that have no interrupt capable GPIO line (e.g. port D on MPC8323), or when interrupt functionality is not used. Update the example to show a scenario where each bank supports a different numbers of IRQs, or no IRQs at all. Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-4-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
2026-08-03dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schemaChristophe Leroy
Convert QE GPIO devicetree binding to DT schema. The old binding uses fsl,<chip>-qe-pario-bank because multiple MCP83XX SoC has support for these GPIO banks. The best practice is to list out every <chip> instead. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-3-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
2026-08-03dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt ↵Paul Louvel
type encoding The QUICC Engine port interrupt controller can be configured to generate an interrupt on either a high-to-low transition or any change in the signal state on the related GPIOs. Update the #interrupt-cells property to 2 so consumers can encode interrupt level information. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-2-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-30 18:15:14 +0000