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2025-07-18dt-bindings: gpio: Convert maxim,max3191x to DT schemaRob Herring (Arm)
Convert the Maxim MAX3191x and similar GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/20250714202843.3011698-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: fsl,qoriq-gpio: Add missing mpc8xxx compatiblesRob Herring (Arm)
The fsl,mpc8349-gpio, fsl,mpc8572-gpio, and fsl,mpc8610-gpio compatibles are already documented in fsl,qoriq-gpio.yaml. Add the additional compatibles that use fsl,mpc8349-gpio as a fallback. With that, the 8xxx_gpio.txt binding document is redundant and can be removed. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Ioana Ciornei <ioana.ciornei@nxp.com> Link: https://lore.kernel.org/r/20250714202941.3013390-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Create a trivial GPIO schemaRob Herring (Arm)
Many simple GPIO controllers without interrupt capability have the same schema other than their compatible value. Combine all these bindings into a single schema. The criteria to be included here is must use 2 cells, have no interrupt capability, have 0 or 1 "reg" entries, and have no other resources (like clocks). Note that "ngpios" is now allowed in some cases it wasn't before and constraints on it have been dropped. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250714201959.2983482-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert st,spear-spics-gpio to DT schemaRob Herring (Arm)
Convert the ST SPEAr SPI CS GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20250714202753.3010240-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert abilis,tb10x-gpio to DT schemaRob Herring (Arm)
Convert the Abilis TB10x GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202934.3013189-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert apm,xgene-gpio-sb to DT schemaRob Herring (Arm)
Convert APM X-Gene Standby GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202821.3011099-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert ti,twl4030-gpio to DT schemaRob Herring (Arm)
Convert the TI TWL4030 PMIC GPIO binding to DT schema format. The number of #interrupt-cells was wrong compared to what is in use. Correct it to be 1. Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202829.3011298-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert lantiq,gpio-mm-lantiq to DT schemaRob Herring (Arm)
Convert the Lantiq SoC External Bus memory mapped GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202837.3011521-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert ti,keystone-dsp-gpio to DT schemaRob Herring (Arm)
Convert the TI Keystone DSP GPIO binding to DT schema format. The "ti,syscon-dev" property was wrong and should be "gpio,syscon-dev" instead. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202850.3011952-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert altr,pio-1.0 to DT schemaRob Herring (Arm)
Convert the altr,pio-1.0 binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202905.3012386-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert cirrus,clps711x-mctrl-gpio to DT schemaRob Herring (Arm)
Convert the cirrus,clps711x-mctrl-gpio binding to DT schema format. Add the missing "gpio,syscon-dev" phandle property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202919.3012764-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert cavium,octeon-3860-gpio to DT schemaRob Herring (Arm)
Convert the Cavium Octeon 3860 GPIO binding to DT schema format. It's a straight forward conversion. Looks like Octeon has no maintainers, so Bartosz is listed. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202927.3012974-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert exar,xra1403 to DT schemaRob Herring (Arm)
Convert XRA1403 16-bit GPIO Expander binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202813.3010879-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert microchip,pic32mzda-gpio to DT schemaRob Herring (Arm)
Convert the Microchip PIC32 GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202807.3010652-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-18dt-bindings: gpio: Convert lacie,netxbig-gpio-ext to DT schemaRob Herring (Arm)
Convert the Lacie NetxBig GPIO binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250714202801.3010442-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-17Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.16-rc7). Conflicts: Documentation/netlink/specs/ovpn.yaml 880d43ca9aa4 ("netlink: specs: clean up spaces in brackets") af52020fc599 ("ovpn: reject unexpected netlink attributes") drivers/net/phy/phy_device.c a44312d58e78 ("net: phy: Don't register LEDs for genphy") f0f2b992d818 ("net: phy: Don't register LEDs for genphy") https://lore.kernel.org/20250710114926.7ec3a64f@kernel.org drivers/net/wireless/intel/iwlwifi/fw/regulatory.c drivers/net/wireless/intel/iwlwifi/mld/regulatory.c 5fde0fcbd760 ("wifi: iwlwifi: mask reserved bits in chan_state_active_bitmap") ea045a0de3b9 ("wifi: iwlwifi: add support for accepting raw DSM tables by firmware") net/ipv6/mcast.c ae3264a25a46 ("ipv6: mcast: Delay put pmc->idev in mld_del_delrec()") a8594c956cc9 ("ipv6: mcast: Avoid a duplicate pointer check in mld_del_delrec()") https://lore.kernel.org/8cc52891-3653-4b03-a45e-05464fe495cf@kernel.org No adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-17dt-bindings: trivial-devices: Add undocumented hwmon devicesRob Herring (Arm)
There's a bunch of undocumented, but already in use trivial hwmon devices. Most are just variants of existing trivial devices. Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20250701-dt-hwmon-compatibles-v1-6-ad99e65cf11b@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-07-17dt-bindings: arm-smmu: Remove sdm845-cheza specific entryKonrad Dybcio
The firmware on SDM845-based Cheza boards did not provide the same level of feature support for SMMUs (particularly around the Adreno GPU integration). Now that Cheza is being removed from the kernel (almost none exist at this point in time), retire the entry as well. Most notably, it's not being marked as deprecated instead, as there is no indication that any more of those ~7 year old devboards will be built. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-3-6fa8d3261813@oss.qualcomm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-07-17dt-bindings: thermal: qcom-tsens: document the Milos Temperature SensorLuca Weiss
Document the Temperature Sensor (TSENS) on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-8-e8f9a789505b@fairphone.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Video Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Video Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos GPU Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Display Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Display Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Camera Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Global Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) Global Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatibleStephan Gerhold
X1E80100 videocc is largely identical to SM8550, but needs slightly different PLL frequencies. Add a separate qcom,x1e80100-videocc compatible to the existing schema used for SM8550. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-1-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos TCSR Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) TCSR Clock Controller. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-3-b49f19055768@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: Document the Milos RPMH Clock ControllerLuca Weiss
Add bindings documentation for the Milos (e.g. SM7635) RPMH Clock Controller. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-1-b49f19055768@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Video clock controllerTaniya Das
Add DT bindings for the Video clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controllerTaniya Das
Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Display clock controllerTaniya Das
Add DT bindings for the Display clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Camera clock controllerTaniya Das
Add DT bindings for the Camera clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into ↵Bjorn Andersson
clk-for-6.17 Merge the IPQ5018 CMN PLL binding through a topic branch, to allow merging the clock defines into DeviceTree branch as well.
2025-07-16dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoCGeorge Moussalem
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatibleLuca Weiss
Document the Milos compatible used to describe the pmic glink on this SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-11-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side ↵Luca Weiss
channel Document the Always-On Subsystem side channel on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-7-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: firmware: qcom,scm: document Milos SCM Firmware InterfaceLuca Weiss
Document the SCM Firmware Interface on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-4-e8f9a789505b@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: net: cdns,macb: Add external REFCLK propertyRyan Wanner
REFCLK can be provided by an external source so this should be exposed by a DT property. The REFCLK is used for RMII and in some SoCs that use this driver the RGMII 125MHz clk can also be provided by an external source. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/d558467c4d5b27fb3135ffdead800b14cd9c6c0a.1752510727.git.Ryan.Wanner@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-16dt-bindings: thermal: rockchip: document otp thermal trimNicolas Frattaroli
Several Rockchip SoCs, such as the RK3576, can store calibration trim data for thermal sensors in OTP cells. This capability should be documented. Such a rockchip thermal sensor may reference cell handles that store both a chip-wide trim for all the sensors, as well as cell handles for each individual sensor channel pointing to that specific sensor's trim value. Additionally, the thermal sensor may optionally reference cells which store the base in terms of degrees celsius and decicelsius that the trim is relative to. Each SoC that implements this appears to have a slightly different combination of chip-wide trim, base, base fractional part and per-channel trim, so which ones do which is documented in the bindings. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-4-b6e9efbf1015@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-07-16dt-bindings: rockchip-thermal: Add RK3576 compatibleNicolas Frattaroli
Add a new compatible for the thermal sensor device on the RK3576 SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-2-b6e9efbf1015@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-07-16dt-bindings: watchdog: nxp,pnx4008-wdt: allow clocks propertyFrank Li
Allow clocks property to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: watchdog@4003c000 (nxp,pnx4008-wdt): Unevaluated properties are not allowed ('clocks' was unexpected) Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250624201227.2515275-1-Frank.Li@nxp.com Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2025-07-16dt-bindings: nvmem: convert vf610-ocotp.txt to yaml formatFrank Li
Convert vf610-ocotp.txt to yaml format. Additional changes: - Remove label in examples. - Add include file in examples. - Move reg just after compatible in examples. - Add ref: nvmem.yaml and nvmem-deprecated-cells.yaml - Remove #address-cells and #size-cells from required list to match existed dts file. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-9-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: mediatek: efuse: split MT8186/MT8188 from base versionChen-Yu Tsai
On MT8186 and MT8188 one of the NVMEM cells contains the GPU speed bin value. In combination with the GPU OPP bindings, on these two platforms there is an implied scheme of converting the cell value to what the GPU OPP "opp-supported-hw" property matches. This does not apply to the base mediatek,efuse hardware, nor does it apply to any of the other platforms that do not have the GPU speed bin cell. The platform maintainer argues that this makes the compatibles incompatible with the base "mediatek,efuse" compatible, as shown in the link given. Deprecate the MT8186/MT8188 + "mediatek,efuse" combination, and add new entries with MT8186 being the base model and MT8188 falling back to MT8186. Link: https://lore.kernel.org/all/11028242-afe4-474a-9d76-cd1bd9208987@collabora.com/ Fixes: ff1df1886f43 ("dt-bindings: nvmem: mediatek: efuse: Add support for MT8188") Cc: Johnson Wang <johnson.wang@mediatek.com> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-8-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: SID: Add binding for A523 SID controllerMikhail Kalashnikov
The SID controller should be compatible with A64 and others SoC with 0x200 offset. Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-7-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: convert lpc1857-eeprom.txt to yaml formatFrank Li
Convert lpc1857-eeprom.txt to yaml format. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-5-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16dt-bindings: nvmem: fixed-layout: Allow optional bit positionsSven Peter
NVMEM nodes can optionally include the bits property to specify the bit position of the cell within a byte. Extend patternProperties to allow adding the bit offset to the node address to be able to distinguish nodes with the same address but different bit positions, e.g. trim@54,4 { reg = <0x54 1>; bits = <4 2>; }; trim@54,0 { reg = <0x54 1>; bits = <0 4>; }; Before the conversion to NVMEM layouts in commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") this extension was originally added with commit 4b2545dd19ed ("dt-bindings: nvmem: Extend patternProperties to optionally indicate bit position") to the now deprecated layout. Signed-off-by: Sven Peter <sven@kernel.org> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250712181905.6738-3-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-16ASoC: dt-bindings: qcom,lpass-va-macro: Define clock-names in top-levelKrzysztof Kozlowski
Device variants use different amount of clock inputs, but all of them are in the same order, 'clock-names' in top-level properties can define the list and each if:then: block can only narrow the number of items. This is preferred syntax, because it keeps list unified among devices and encourages adding new entries to the end of the list, instead of adding them in the middle. The change has no functional impact, but partially reverts approach implemented in commit cfad817095e1 ("ASoC: dt-bindings: qcom,lpass-va-macro: Add missing NPL clock"). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250716074957.102402-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-07-16dt-bindings: display: Add Sitronix ST7567 LCD ControllerJavier Martinez Canillas
Sitronix ST7567 is a monochrome Dot Matrix LCD Controller. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Marcus Folkesson <marcus.folkesson@gmail.com> Link: https://lore.kernel.org/r/20250715110411.448343-5-javierm@redhat.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-07-16dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920Sowon Na
Add hsi2 compatible for ExynosAutov920 ufs shareability register to set io coherency of the ExynosAutov920 ufs. Signed-off-by: Sowon Na <sowon.na@samsung.com> Link: https://lore.kernel.org/r/20250702013316.2837427-4-sowon.na@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-07-15spi: dt-bindings: spi-mux: Drop "spi-max-frequency" as requiredRob Herring (Arm)
There's little reason to require the SPI mux to define a maximum bus frequency as the muxing is just the chip select and devices still define their maximum freq. In fact, several users don't set "spi-max-frequency" which caused warnings. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://patch.msgid.link/20250715202711.1882103-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-07-15dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port nodeKrishna Chaitanya Chundru
Move the phys, phy-names, reset-gpios properties to the PCIe Root Port node from Host Bridge node, as agreed upon here [1]. Update the qcom,pcie-common.yaml to include the 'phys' property in the Root Port node. 'phy-names' property is not needed in Root Port since each Root Port supports only one PHY. Also, there is already 'reset-gpios' property defined for PERST# in pci-bus-common.yaml, so use that property instead of 'perst-gpios'. For backward compatibility, do not remove any existing properties in the bridge node, but mark them as 'deprecated' instead. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> [mani: commit message rewording] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250702-perst-v5-1-920b3d1f6ee1@qti.qualcomm.com
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