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Reference the common power supply schema to bring the definition of
monitored-battery property. Drop also the obvious description because
it is duplicating what is in power-supply.yaml.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250604-dt-bindings-psy-monitored-battery-v1-1-7f755ff75218@linaro.org
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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This documents Firefly ROC-RK3588S-PC which is a SBC based on RK3588S SoC.
Link: https://wiki.t-firefly.com/en/Station-M3/index.html
Signed-off-by: Hsun Lai <i@chainsx.cn>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250609113044.8846-2-i@chainsx.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The '#reset-cells' property is permitted for some of the MT8188
clock controllers, but not listed as a valid property.
Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add a compatible for the MediaTek MT8370 SoC, with an
integrated ARM Mali G57 MC2 GPU (Valhall-JM, dual core).
None of the already existing SoC specific compatibles is usable as
fallback, as those either do not match the number of cores (and number
of power domains), or are for a different GPU architecture.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250509-mt8370-enable-gpu-v6-1-2833888cb1d3@collabora.com
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Add compatible strings "nxp,imx95-jpgdec" and "nxp,imx95-jpgenc", which
are backward compatible with "nxp,imx8qxp-jpgdec" and
"nxp,imx8qxp-jpegenc". i.MX95 just need one power domain which combine
wrap and all slots together. Reduce minItems of power-domains to 1 for
i.MX95 and keep the same restriction for others.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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Convert fsl-vdoa.txt to yaml format.
Additional changes:
- Add irq.h and imx6qdl-clock.h in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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Document the GPI DMA engine on the sc8280xp platform.
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250617090032.1487382-2-mitltlatltl@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Convert lpc1850-ccu.txt to yaml format.
Additional changes:
- remove label in examples.
- remove clock consumer in examples.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250602141937.942091-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Cross-merge networking fixes after downstream PR (net-6.16-rc3).
No conflicts or adjacent changes.
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Renesas RZ/N2H DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
SoC, shared by driver and DT source files.
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Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add RZ/N2H (R9A09G087), its variants, and the rzn2h-evk evaluation board
in documentation.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/N2H (R9A09G087) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC. Therefore, "renesas,r9a09g077-rsci"
is used as a fallback compatible string for RZ/N2H.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250609192344.293317-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Document the Renesas USBHS controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The USBHS block on RZ/V2N is functionally identical to
the one on the RZ/G2L family, so no driver changes are needed. The
existing "renesas,rzg2l-usbhs" fallback compatible will continue to be
used for handling this IP.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250528133440.168133-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Document the compatible strings for the Moduline Display controller.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add an interrupt property to the device tree bindings for the TI TPS23881
PSE controller. The interrupt is primarily used to detect classification
and disconnection events, which are essential for managing the PSE
controller in compliance with the PoE standard.
Interrupt support is essential for the proper functioning of the TPS23881
controller. Without it, after a power-on (PWON), the controller will
no longer perform detection and classification. This could lead to
potential hazards, such as connecting a non-PoE device after a PoE device,
which might result in magic smoke.
Signed-off-by: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250617-feature_poe_port_prio-v14-13-78a1a645e2ee@bootlin.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Adds the regulator supply parameter of the managers.
Update also the example as the regulator supply of the PSE PIs
should be the managers itself and not an external regulator.
Signed-off-by: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250617-feature_poe_port_prio-v14-11-78a1a645e2ee@bootlin.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Convert the Alphascale Clock Controller binding to DT schema format.
Add the undocumented 'clocks' property which is used in DTS. Drop the
clock defines and consumer examples from the old binding.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004712.1793193-1-robh@kernel.org
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell Armada 3xx Core Divider clock binding to DT schema
format.
Add the missing "marvell,armada-390-corediv-clock" compatible and
"clock-output-names" property.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521211840.77487-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell Armada 3700 peripheral clock binding to DT schema
format. The north bridge is also a "syscon", so add the compatible to
it.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521211826.77098-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell SoC core clock binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210844.62613-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell Berlin2 clock binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210839.62409-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell Dove PLL divider clock binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210832.62177-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell Armada 3700 TBG clock binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210826.61957-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell gating clock binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210813.61484-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Marvell Armada XP CPU clock binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210806.61286-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the TI-NSPIRE clock bindings to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210750.60759-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Intel/LSI AXM5516 clock binding to DT schema format. It's
a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210741.60467-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521210712.59742-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Broadcom BCM2835 CPRMAN clock binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004625.1791913-1-robh@kernel.org
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
[sboyd@kernel.org: Add list to maintainers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Cirrus EP7xxx (aka CLPS711x) binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004923.1795927-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the APM XGene clocks to DT schema. The device clock binding is
a bit different from the others, so put it in its own schema file.
Drop the examples.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004655.1792703-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Axis ARTPEC-6 clock controller to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004647.1792464-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Convert the Broadcom BCM53573 ILP clock binding to DT schema format.
It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250521004618.1791669-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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into clk-for-6.17
Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.
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The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.
Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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BQ Aquaris X5 Plus (Longcheer L9360) is a smartphone based on MSM8976
SoC.
Signed-off-by: André Apitzsch <git@apitzsch.eu>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250615-bqx5plus-v2-2-72b45c84237d@apitzsch.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The cs42xx8 codecs may be used with audio graph card and thus may require
an additional property: 'port'. Add it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20250617144619.1130857-1-laurentiumihalcea111@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add the compatible for the pmu mfd on RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250518220707.669515-4-jonas@kwiboo.se
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add the compatible string and power domains for RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250518220707.669515-2-jonas@kwiboo.se
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add EIC7700 pinctrl device for all configurable pins.
For the EIC7700 pinctrl registers, each register (32 bits)
controls the characteristics of a single pin.
It supports setting function multiplexing, Schmitt trigger,
drive strength, pull-up/pull-down, and input enable.
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20250612104811.1206-1-luyulin@eswincomputing.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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It is possible that the PL061 doesn't have any interrupt connected and
can't be an interrupt provider, so drop the interrupt properties as
required.
The LG LG131x SoCs are one example of this.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250609220900.3035642-1-robh@kernel.org
[Bartosz: g/pl011/pl061/]
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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Document the RSVD (Reserved) mux function, used to reserve pins
for a coprocessor not running Linux.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20250610152309.299438-3-antonio.borneo@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Convert nxp-spifi.txt to yaml format.
Additional changes:
- ref /schemas/spi/spi-controller.yaml.
- remove label in example.
- change node name to spi in example.
- remove child node in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove
fsl,mipi-phy-gpr from required properties and add new reg space, since
i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space.
Keep the same restriction for other compatible strings.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250522-8qxp_camera-v5-8-d4be869fdb7e@nxp.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names,
power-domains, and ports differ significantly from the existing
nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches.
Add new file to MAINTAINERS.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250522-8qxp_camera-v5-1-d4be869fdb7e@nxp.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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Currently described or not, IMEM is present on *all* Qualcomm SoCs.
Preemptively add a number of compatibles to ease integration.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250523-topic-ipa_mem_dts-v1-1-f7aa94fac1ab@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for 6.17:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- atomic-helpers: Tune the enable / disable sequence
- bridge: Add destroy hook
- color management: Add helpers for hardware gamma LUT handling
- HDMI: Add CEC handling, YUV420 output support
- sched: tracing improvements
Driver Changes:
- hyperv: Move out of simple-kms, drm_panic support
- i915: drm_panel_follower support
- imx: Add IMX8qxq Display Controller Support
- lima: Add Rockchip RK3528 GPU Support
- nouveau: fence handling cleanup
- panfrost: Add BO labeling, 64-bit registers access
- qaic: Add RAS Support
- rz-du: Add RZ/V2H(P) Support, MIPI-DSI DCS Support
- sun4i: Add H616 Support
- tidss: Add TI AM62L Support
- vkms: YUV and R* formats support
- bridges:
- Switched to reference counted drm_bridge allocations
- panels:
- Switched to reference counted drm_panel allocations
- Add support for fwnode-based panel lookup
- himax-hx8394: Support for Huiling hl055fhv028c
- ilitek-ili9881c: Support for 7" Raspberry Pi 720x1280
- panel-edp: Support for KDC KD116N3730A05, N160JCE-ELL CMN,
- panel-simple: Support for AUO P238HAN01
- st7701: Support for Winstar wf40eswaa6mnn0
- visionox-rm69299: Support for rm69299-shift
- New panels: Renesas R61307, Renesas R69328
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maxime Ripard <mripard@redhat.com>
Link: https://lore.kernel.org/r/20250612-coucal-of-impossible-cleaning-a5eecf@houat
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git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm
Pull libnvdimm fix from Ira Weiny:
"This converts the pmem-region device tree bindings to YAML to fix
errors and bring it up to date"
* tag 'libnvdimm-fixes-6.16-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm:
dt-bindings: pmem: Convert binding to YAML
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Document Kryo 470 CPUs found in Qualcomm Snapdragon 730/730G/732G
(SM7150).
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20250422-sm7150-upstream-v1-1-bf9a9081631d@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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