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2026-03-25Merge branch 'ib-scmi-pinctrl-gpio' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into gpio/for-next Pull in the SCMI GPIO driver along with its pinctrl dependencies.
2026-03-25dt-bindings: mmc: sdhci-of-aspeed: Add AST2700 compatibleRyan Chen
AST2700 SDHCI controller is fully compatible with AST2600. However, it is necessary to take the AST2700 SD controller out of reset, so require the 'resets' property. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-25dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XPPengyu Luo
Document DSI controller and DSI phy on SC8280XP platform. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/709947/ Link: https://lore.kernel.org/r/20260308064835.479356-4-mitltlatltl@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display/msm: dsi-controller-main: Add SC8280XPPengyu Luo
Since SC8280XP and SA8775P have the same DSI version(2.5.1), then we fallback to SA8775P compatible. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/709944/ Link: https://lore.kernel.org/r/20260308064835.479356-3-mitltlatltl@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XPPengyu Luo
Since SC8280XP and SA8775P have the same values for the REVISION_ID registers, then we fallback to SA8775P compatible. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/709943/ Link: https://lore.kernel.org/r/20260308064835.479356-2-mitltlatltl@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display/msm: qcom,eliza-mdss: Add Eliza SoCKrzysztof Kozlowski
Add MDSS/MDP display subsystem for Qualcomm Eliza SoC, being overall a minor revision change against SM8750, but coming with few different components, like different DSI PHY, missing DP1 and added HDMI. The binding does not include HDMI description yet. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708878/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-5-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display/msm: qcom,sm8650-dpu: Add Eliza SoCKrzysztof Kozlowski
Add DPU (v12.4) for Qualcomm Eliza SoC which has noticeable differences against SM8750 (v12.0) of mostly removing blocks: - INTF_3 paired with INTF_0 (no DP1), - Removed CTL4-5 blocks, - Removed VIG2-3 and DMA4-5, - Removed LM4-7, DSPP3, PINGPONG4-7, MERGE4-5 and several DSC blocks, - Added HDMI interface. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708872/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-4-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display/msm: dsi-controller-main: Add Eliza SoCKrzysztof Kozlowski
Add DSI controller Qualcomm Eliza SoC using exactly the same block as SM8750. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/708867/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-3-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display/msm: dsi-phy-7nm: Add Eliza SoCKrzysztof Kozlowski
Add DSI PHY 4nm v5.2.4 for the Qualcomm Eliza SoC, fully compatible with SM8650. Note that this DSI PHY, unlike the Eliza MDSS DSI, is not compatible with SM8750. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/708866/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-2-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-25dt-bindings: display/msm: dp-controller: Add Eliza SoCKrzysztof Kozlowski
Add DisplayPort controller for Qualcomm Eliza SoC fully compatible with SM8650. The device looks very similar to SM8750 (same DP TX block v1.5.1) but with a differences in DP PHY: Eliza and SM8650 use DP PHY 4nm v7.0, SM8750 uses 3nm v8.0. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/708864/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-1-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-24dt-bindings: clock, reset: Add econet EN751221Caleb James DeLisle
Add clock and reset bindings for EN751221 as well as a "chip-scu" which is an additional regmap that is used by the clock driver as well as others. This split of the SCU across two register areas is the same as the Airoha AN758x family. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-03-24dt-bindings: input: matrix-keymap: fix key board wordingHugo Villeneuve
The correct wording is keyboard, without a space. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Link: https://patch.msgid.link/20260323140024.104475-1-hugo@hugovil.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-24Merge commit 'f35dbac6942171dc4ce9398d1d216a59224590a9' into ↵Steven Rostedt
trace/ring-buffer/core The commit f35dbac69421 ("ring-buffer: Fix to update per-subbuf entries of persistent ring buffer") was a fix and merged upstream. It is needed for some other work in the ring buffer. The current branch has the remote buffer code that is shared with the Arm64 subsystem and can't be rebased. Merge in the upstream commit to allow continuing of the ring buffer work. Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
2026-03-24dt-bindings: clock: eswin: Documentation for eic7700 SoCXuyang Dong
Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.dev> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-03-24dt-bindings: input: touchscreen: edt-ft5x06: Add FocalTech FT3519Bhushan Shah
Document FocalTech FT3519 support by adding the compatible. It's 10 point touchscreen, which is compatible with FT3518 Signed-off-by: Bhushan Shah <bhushan.shah@machinesoul.in> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260314-edt-ft3519-v3-1-5ee91b408ed6@machinesoul.in Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-24dt-bindings: arm: rockchip: Add Khadas Edge 2L boardGray Huang
The Khadas Edge 2L is a single board computer based on the Rockchip RK3576 SoC. Specification: - Rockchip RK3576 - 8/16GB LPDDR5 - 64/128GB eMMC 5.1 - AP6275P WiFi6 LAN - HDMI2.1 Type-A - MIPI-CSI x2 - MIPI-DSI x2 - USB3.1; USB2.0 - RTC clock - PWM fan - SPI Flash - Pads expansion board (UART, USB) Signed-off-by: Gray Huang <gray.huang@wesion.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260317090731.600787-2-gray.huang@wesion.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-03-24media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible stringGuoniu Zhou
The CSI-2 receiver in the i.MX8ULP is almost identical to the version present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk clock as the input clock for its APB interface of Control and Status register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and increase maxItems of Clocks (clock-names) to 4 from 3. And keep the same restriction for existing compatible. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> Link: https://patch.msgid.link/20251205-csi2_imx8ulp-v10-1-190cdadb20a3@nxp.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-03-24media: dt-bindings: nxp,imx8-isi: Add i.MX95 ISI compatible stringGuoniu Zhou
The ISI module on i.MX95 supports up to eight channels and four link sources to obtain the image data for processing in its pipelines. It can process up to eight image sources at the same time. Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251105-isi_imx95-v3-1-3987533cca1c@nxp.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-03-24Merge tag 'v7.0-rc5' into nextDmitry Torokhov
Sync up with mainline to pull in a fix for smb compilation error.
2026-03-24docs: Raise minimum pahole version to 1.26 for KF_IMPLICIT_ARGS kfuncszhidao su
Since Linux 7.0, kfuncs annotated with KF_IMPLICIT_ARGS require pahole v1.26 or later. Without it, such kfuncs will have incorrect BTF prototypes in vmlinux, causing BPF programs to fail to load with a "func_proto incompatible with vmlinux" error. Many sched_ext kfuncs are affected (e.g. scx_bpf_create_dsq, scx_bpf_kick_cpu). The root cause: scripts/Makefile.btf passes --btf_features=decl_tag_kfuncs to pahole only when pahole >= 1.26. Without that flag, pahole emits no DECL_TAG BTF entries for __bpf_kfunc-annotated functions. As a result, resolve_btfids/main.c::collect_kfuncs() finds no bpf_kfunc DECL_TAGs, short-circuits at line 1002, and btf2btf() never creates the _impl variants or strips the implicit 'aux' argument from the visible proto. The vmlinux BTF retains the 3-param prototype while BPF programs declare the 2-param version, triggering the mismatch. Raise the minimum version in the requirements table from 1.22 to 1.26 and add a note explaining the failure mode, so users understand why their BPF programs fail on distributions shipping pahole v1.25 (e.g. Ubuntu 24.04 LTS). Suggested-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: zhidao su <suzhidao@xiaomi.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2026-03-24landlock: Expand restrict flags example for ABI version 8Panagiotis "Ivory" Vasilopoulos
Add LANDLOCK_RESTRICT_SELF_TSYNC to the backwards compatibility example for restrict flags. This introduces completeness, similar to that of the ruleset attributes example. However, as the new example can impact enforcement in certain cases, an appropriate warning is also included. Additionally, I modified the two comments of the example to make them more consistent with the ruleset attributes example's. Signed-off-by: Panagiotis "Ivory" Vasilopoulos <git@n0toose.net> Co-developed-by: Dan Cojocaru <dan@dcdev.ro> Signed-off-by: Dan Cojocaru <dan@dcdev.ro> Reviewed-by: Günther Noack <gnoack@google.com> Link: https://lore.kernel.org/r/20260304-landlock-docs-add-tsync-example-v4-1-819a276f05c5@n0toose.net [mic: Update date, improve comments consistency, fix newline issue] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-03-24regulator: da91xx: Allow caching of buck registers when no GPIO input ↵Mark Brown
control is configured André Svensson <andre.svensson@axis.com> says: This series introduces a boolean DT property, dlg,no-gpio-control, for the DA91xx regulators. Use this property to indicate that GPIO control is not configured with the functions DVC/RELOAD/EN, allowing buck registers to be cached. The DA9121 driver checks dlg,no-gpio-control and updates regmap_config's volatile_table if the property is present. Buck registers are removed from the volatile_table if the property is present, enabling caching of the registers, which removes I2C reads when performing an I2C write to the buck registers. Link: https://patch.msgid.link/20260320-no-gpio-control-v2-0-dbc938e462cb@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-24regulator: dt-bindings: dlg,da9121: Add dlg,no-gpio-controlAndré Svensson
Add the optional boolean property dlg,no-gpio-control. When present, it indicates that no DA91xx GPIO pins are configured/used with functions RELOAD/DVC/EN, which can affect the output voltage control, regulator mode control and enable signal control. The absence of relevant GPIO DT properties does not imply that the RELOAD/DVC/EN GPIO functions are unused. These functions are provided by DA91xx GPIO pins and may be controlled by external hardware without corresponding GPIO DT properties. The dlg,no-gpio-control property explicitly indicates that none of these GPIO functions are used. It is mutually exclusive with enable-gpios, regardless of whether the referenced GPIO is connected to a GPIO pin or the IC_EN pin, since enable-gpios allows the regulator to be controlled via an external hardware signal. Co-developed-by: Waqar Hameed <waqar.hameed@axis.com> Signed-off-by: Waqar Hameed <waqar.hameed@axis.com> Signed-off-by: André Svensson <andre.svensson@axis.com> Link: https://patch.msgid.link/20260320-no-gpio-control-v2-1-dbc938e462cb@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-24dt-bindings: riscv: Add Supm extension descriptionGuodong Xu
Add description for the Supm extension. Supm indicates support for pointer masking in user mode. Supm is mandatory for RVA23S64. Add dependency check that Supm requires either Smnpm or Ssnpm. The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-03-24dt-bindings: riscv: microchip: document the PIC64GX curiosity kitPierre-Henry Moussay
Update devicetree bindings document with PIC64GX Curiosity Kit, known by its "Curiosity-GX1000" product code. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-03-24dt-bindings: timer: sifive,clint: add pic64gx compatibilityPierre-Henry Moussay
As mention in sifive,clint.yaml, a specific compatible should be used for pic64gx, so here it is. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-03-24dt-bindings: timer: fsl,imxgpt: add compatible string fsl,imx25-epitFrank Li
Add compatible string fsl,imx25-epit to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb: /soc/bus@53f00000/timer@53f94000: failed to match any schema with compatible: ['fsl,imx25-epit'] Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260211214947.3705328-1-Frank.Li@nxp.com
2026-03-24ASoC: Merge up fixesMark Brown
Merge branch 'for-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-7.1 to get fixes into our development branch and resolve interactions with the match tables.
2026-03-24f2fs: Add defrag_blocks sysfs nodeliujinbao1
Add the defrag_blocks sysfs node to track the amount of data blocks moved during filesystem defragmentation. Signed-off-by: Sheng Yong <shengyong1@xiaomi.com> Signed-off-by: liujinbao1 <liujinbao1@xiaomi.com> Reviewed-by: Chao Yu <chao@kernel.org> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
2026-03-24dt-bindings: arm: rockchip: Add Omega4 Evaluation boardFabio Estevam
Onion Omega4 board is a board based on the RV1103B SoC. Document its compatible. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260313131058.708361-3-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-03-24dt-bindings: soc: rockchip: grf: Add RV1103B compatiblesFabio Estevam
Add the PMU GRF and IOC compatible strings for the RV1103B SoC. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260313131058.708361-1-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-03-24dt-bindings: display: arm,komeda: add Arm China Linlon D6 compatibleCunyuan Liu
Add the Arm China Linlon D6 display controller compatible string. Linlon D6 is register-compatible with Mali-D71, so describe it as a vendor-specific compatible with a fallback to "arm,mali-d71". Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Cunyuan Liu <cunyuan.liu@cixtech.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patch.msgid.link/20260313033119.33686-3-cunyuan.liu@cixtech.com
2026-03-24dt-bindings: vendor-prefixes: Add Arm Technology (China) Co., Ltd.Cunyuan Liu
Add "armchina" vendor prefix for Arm Technology (China) Co., Ltd. Link: https://www.armchina.com/ Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Cunyuan Liu <cunyuan.liu@cixtech.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patch.msgid.link/20260313033119.33686-2-cunyuan.liu@cixtech.com
2026-03-24ASoc: uda1380: Improve error reportingMark Brown
Wenyuan Li <2063309626@qq.com> says: The driver currently ignores the return values of several I2C operations during register writes, which could lead to silent failures and inconsistent device state. Link: https://patch.msgid.link/tencent_579D057AC557914CF739A2D9EAD045CE7306@qq.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-24hwmon: (peci/cputemp) Fix crit_hyst returning delta instead of absolute ↵Sanman Pradhan
temperature The hwmon sysfs ABI expects tempN_crit_hyst to report the temperature at which the critical condition clears, not the hysteresis delta from the critical limit. The peci cputemp driver currently returns tjmax - tcontrol for crit_hyst_type, which is the hysteresis margin rather than the corresponding absolute temperature. Return tcontrol directly, and update the documentation accordingly. Fixes: bf3608f338e9 ("hwmon: peci: Add cputemp driver") Cc: stable@vger.kernel.org Signed-off-by: Sanman Pradhan <psanman@juniper.net> Link: https://lore.kernel.org/r/20260323002352.93417-2-sanman.pradhan@hpe.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2026-03-24iommu/arm-smmu-v3: Update Arm errataRobin Murphy
MMU-700 r1p1 has subsequently fixed some of the errata for which we've been applying the workarounds unconditionally, so we can now make those conditional. However, there have also been some more new cases identified where we must rely on range invalidation commands, and thus still nominally avoid DVM being inadvertently enabled. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24platform/x86: bitland-mifs-wmi: Add new Bitland MIFS WMI driverMingyou Chen
Add a new driver for Bitland laptops that utilize the MIFS (MiInterface) WMI interface. The driver implements several features through the WMI interface: - Platform Profile: Supports "Quiet", "Balanced", "Performance", and "Full Speed" modes. The "Full Speed" mode is intelligently restricted based on the AC adapter type (requires DC power, not supported on USB-C charging) as required by the hardware. - Hwmon: Provides monitoring for CPU, GPU, and System fan speeds, as well as CPU temperature sensors. - Keyboard Backlight: Integrated with the LED class device for brightness control and provides sysfs attributes for keyboard modes (cyclic, fixed, etc.). - GPU Mode: Allows switching between Hybrid, Discrete, and UMA graphics modes via sysfs. - Hotkeys: Handles WMI events for system hotkeys (Calculator, Browser, App launch) using sparse keymaps and reports status changes for Airplane mode, Touchpad, and CapsLock. - Fan Boost: Provides a sysfs interface to force fans to maximum speed. The driver registers two WMI GUIDs: - B60BFB48-3E5B-49E4-A0E9-8CFFE1B3434B: Control methods - 46C93E13-EE9B-4262-8488-563BCA757FEF: Event notifications Reviewed-by: Armin Wolf <W_Armin@gmx.de> Signed-off-by: Mingyou Chen <qby140326@gmail.com> Link: https://patch.msgid.link/20260323132218.444383-1-qby140326@gmail.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
2026-03-24ASoC: dt-bindings: stm32: Fix incorrect compatible string in stm32h7-sai matchJihed Chaibi
The conditional block that defines clock constraints for the stm32h7-sai variant references "st,stm32mph7-sai", which does not match any compatible string in the enum. As a result, clock validation for the h7 variant is silently skipped. Correct the compatible string to "st,stm32h7-sai". Fixes: 8509bb1f11a1f ("ASoC: dt-bindings: add stm32mp25 support for sai") Signed-off-by: Jihed Chaibi <jihed.chaibi.dev@gmail.com> Reviewed-by: Olivier Moysan <olivier.moysan@foss.st.com> Link: https://patch.msgid.link/20260321012011.125791-1-jihed.chaibi.dev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-24Merge branch 'ib-scmi-pinctrl-gpio' into develLinus Walleij
2026-03-24gpio: dt-bindings: Add GPIO on top of generic pin controlAKASHI Takahiro
Traditionally, firmware will provide a GPIO interface or a pin control interface. However, the SCMI protocol provides a generic pin control interface and the GPIO support is built on top of that using the normal pin control interfaces. Potentially, other firmware will adopt a similar generic approach in the future. Document how to configure the GPIO device. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-03-24perf: add NVIDIA Tegra410 C2C PMUBesar Wicaksono
Adds NVIDIA C2C PMU support in Tegra410 SOC. This PMU is used to measure memory latency between the SOC and device memory, e.g GPU Memory (GMEM), CXL Memory, or memory on remote Tegra410 SOC. Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24perf: add NVIDIA Tegra410 CPU Memory Latency PMUBesar Wicaksono
Adds CPU Memory (CMEM) Latency PMU support in Tegra410 SOC. The PMU is used to measure latency between the edge of the Unified Coherence Fabric to the local system DRAM. Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24perf/arm_cspmu: nvidia: Add Tegra410 PCIE-TGT PMUBesar Wicaksono
Adds PCIE-TGT PMU support in Tegra410 SOC. This PMU is instanced in each root complex in the SOC and it captures traffic originating from any source towards PCIE BAR and CXL HDM range. The traffic can be filtered based on the destination root port or target address range. Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24perf/arm_cspmu: nvidia: Add Tegra410 PCIE PMUBesar Wicaksono
Adds PCIE PMU support in Tegra410 SOC. This PMU is instanced in each root complex in the SOC and can capture traffic from PCIE device to various memory types. This PMU can filter traffic based on the originating root port or BDF and the target memory types (CPU DRAM, GPU Memory, CXL Memory, or remote Memory). Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24perf/arm_cspmu: nvidia: Add Tegra410 UCF PMUBesar Wicaksono
The Unified Coherence Fabric (UCF) contains last level cache and cache coherent interconnect in Tegra410 SOC. The PMU in this device can be used to capture events related to access to the last level cache and memory from different sources. Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24perf/arm_cspmu: nvidia: Rename doc to Tegra241Besar Wicaksono
The documentation in nvidia-pmu.rst contains PMUs specific to NVIDIA Tegra241 SoC. Rename the file for this specific SoC to have better distinction with other NVIDIA SoC. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-03-24media: dt-bindings: ovti,ov8856: Allow orientation & rotation propsAlexander Koskovich
Allow the orientation and rotation properties from video-interface-devices to be specified. The sensor can be front or rear facing and can be mounted at any rotation. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-03-24dt-bindings: media: st,stm32-dcmi: add 'power-domains' propertyAlain Volmat
STM32 DCMI may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 DCMI. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-03-24media: uapi: Clarify MBUS color component order for serial busesMaxime Ripard
The subdev format documentation has a subsection describing how to use the media bus pixel codes for serial buses. While it describes the sampling part well, it doesn't really describe the current convention used for the components order. Let's improve that. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-03-24dt-bindings: PCI: cix,sky1-pcie-host: Add power-domainsGary Yang
The Sky1 PCIe controller resides in a dedicated power domain managed via SCMI. Add the power-domains property to the binding to allow describing this dependency. Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260313114914.1564115-2-gary.yang@cixtech.com
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-10 02:49:47 +0000