summaryrefslogtreecommitdiff
path: root/Documentation
AgeCommit message (Collapse)Author
2026-01-09ASoC: dt-bindings: realtek,rt5640: Document mclkJon Hunter
Commit eba5a0bac211 ("ASoC: dt-bindings: realtek,rt5640: Convert to dtschema") converted the rt5640 dt-binding to yaml format but in the process dropped 'clock' and 'clock-names' properties that are used to specify the codec 'mclk'. This is causing DTB build warnings for boards that use this codec and define an 'mclk' in device-tree. Update the rt5640 binding document to add the optional mclk. Fixes: eba5a0bac211 ("ASoC: dt-bindings: realtek,rt5640: Convert to dtschema") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260108143158.351223-2-jonathanh@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-09dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have IRQ-capable pins handled by the ICU, which forwards them to the GIC. The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily, and the mapping is not configurable. Document the required properties to handle GPIO IRQ. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09dt-bindings: pinctrl: intel: keembay: fix typoAkiyoshi Kurita
Fix a typo in the documentation ("upto" -> "up to"). Signed-off-by: Akiyoshi Kurita <weibu@redadmin.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-09dt-bindings: arm: at91: add lan966 pcb8385 boardHoratiu Vultur
Add documentation for Microchip LAN9668 PCB8385 Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20251208083545.3642168-2-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-09Merge tag 'drm-misc-next-2026-01-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.20: UAPI Changes: Cross-subsystem Changes: Core Changes: - draw: Add API to check if a format conversion can be done - panic: Rename draw_panic_static_* to draw_panic_screen_*, Add kunit tests - shmem: Improve tests Driver Changes: - ast: Big endian fixes - etnaviv: Add PPU flop reset support - panfrost: Add GPU_PM_RT support for RZ/G3E SoC - panthor: multiple fixes around VM termination, huge page support - pl111: Fix build regression - v3d: Fix DMA segment size - bridge: - Add connector argument to .hpd_notify - Plenty of patches to convert existing drivers to refcounting - Convert Rockchip's inno hdmi support to a proper bridge - lontium-lt9611uxc: Switch to HDMI audio helpers - panel: - New panel: BOE NV140WUM-T08 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://patch.msgid.link/20260108-literate-nyala-of-courtesy-de501a@houat
2026-01-09dmaengine: idxd: Expose DSA3.0 capabilities through sysfsYi Sun
Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA) capability registers (dsacap0-2) to enable userspace awareness of hardware features in DSA version 3 and later devices. Userspace components (e.g. configure libraries, workload Apps) require this information to: 1. Select optimal data transfer strategies based on SGL capabilities 2. Enable hardware-specific optimizations for floating-point operations 3. Configure memory operations with proper numerical handling 4. Verify compute operation compatibility before submitting jobs The output format is <dsacap2>,<dsacap1>,<dsacap0>, where each DSA capability value is a 64-bit hexadecimal number, separated by commas. The ordering follows the DSA 3.0 specification layout: Offset: 0x190 0x188 0x180 Reg: dsacap2 dsacap1 dsacap0 Example: cat /sys/bus/dsa/devices/dsa0/dsacaps 000000000000f18d,0014000e000007aa,00fa01ff01ff03ff According to the DSA 3.0 specification, there are 15 fields defined for the three dsacap registers. However, there's no need to define all register structures unless a use case requires them. At this point, support for the Scatter-Gather List (SGL) located in dsacap0 is necessary, so only dsacap0 is defined accordingly. For reference, the DSA 3.0 specification is available at: Link: https://software.intel.com/content/www/us/en/develop/articles/intel-data-streaming-accelerator-architecture-specification.html Signed-off-by: Yi Sun <yi.sun@intel.com> Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> Link: https://patch.msgid.link/20260107-idxd-yi-sun-dsa3-sgl-size-v2-1-dbef8f559e48@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dt-bindings: soc: spacemit: k3: add clock supportYixun Lan
Add compatible strings for clock drivers to support Spacemit K3 SoC, also includes all the defined clock IDs. The SpacemiT K3 SoC clock IP is scattered over several different blocks, which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of generating clock and reset signals. APMU and MPMU have additional Power Domain management functionality. Following is a brief list that shows devices managed in each block: APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN APBS: various PPL clocks control APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. DCID: SRAM, DMA, TCM MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-08dt-bindings: net: dsa: microchip: Make pinctrl 'reset' optionalFrank Li
Commit e469b87e0fb0d ("dt-bindings: net: dsa: microchip: Add strap description to set SPI mode") required both 'default' and 'reset' pinctrl states for all compatible devices. However, this requirement should be only applicable to KSZ8463. Make the 'reset' pinctrl state optional for all other Microchip DSA devices while keeping it mandatory for KSZ8463. Fix below CHECK_DTBS warnings: arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dtb: switch@5f (microchip,ksz9893): pinctrl-names: ['default'] is too short from schema $id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260106143620.126212-1-Frank.Li@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-08KVM: x86/pmu: Expose enable_mediated_pmu parameter to user spaceDapeng Mi
Expose enable_mediated_pmu parameter to user space, i.e. allow userspace to enable/disable mediated vPMU support. Document the mediated versus perf-based behavior as part of the kernel-parameters.txt entry, and opportunistically add an entry for the core enable_pmu param as well. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Mingwei Zhang <mizhang@google.com> Tested-by: Xudong Hao <xudong.hao@intel.com> Co-developed-by: Sean Christopherson <seanjc@google.com> Tested-by: Manali Shukla <manali.shukla@amd.com> Link: https://patch.msgid.link/20251206001720.468579-34-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-01-08Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.19-rc5). No conflicts, or adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-08dt-bindings: display: rockchip,vop: Add compatible for rk3506Chaoyi Chen
The rk3506 VOP has adopted a new implementation. Add a new compatible string for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251106020632.92-5-kernel@airkyi.com
2026-01-08dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506Chaoyi Chen
Document a compatible string for the rk3506 mipi-dsi. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251106020632.92-4-kernel@airkyi.com
2026-01-08Documentation: tracing: Add PCI tracepoint documentationShuai Xue
The PCI tracing system provides tracepoints to monitor critical hardware events that can impact system performance and reliability. Add documentation about it. Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com> [bhelgaas: squash fixes: https://lore.kernel.org/r/20260108013956.14351-2-bagasdotme@gmail.com https://lore.kernel.org/r/20260108013956.14351-3-bagasdotme@gmail.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://patch.msgid.link/20251210132907.58799-4-xueshuai@linux.alibaba.com
2026-01-08dt-bindings: arm: mediatek: Add Ezurio Tungsten entriesGary Bisson
Add device tree bindings support for the Ezurio Tungsten 510 (MT8370) SMARC [1] / Ezurio Tungsten 700 (MT8390) SMARC [2] + Universal SMARC carrier board [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/product/tungsten700-smarc [3] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-08dt-bindings: vendor-prefixes: Add Ezurio LLCGary Bisson
Ezurio is the new name of Laird Connectivity after it acquired Boundary Devices. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-08dt-bindings: leds: Add LP5860 LED controllerSteffen Trumtrar
The LP5860 is a LED matrix driver with 18 constant current sinks and 11 scan switches for 198 LED dots: * Supply range from 2.7 V to 5.5 V * 0.1mA - 50mA per current sink * 1MHz I2C and 12MHz SPI control interface * 8-bit analog dimming * 8/16-bit PWM dimming * individual ON and OFF control for each LED dot * globat 3-bit Maximum Current setting for all LED dots * individual LED dot open/short detection Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251201-v6-14-topic-ti-lp5860-v6-1-be9a21218157@pengutronix.de Signed-off-by: Lee Jones <lee@kernel.org>
2026-01-08Documentation: gpio: pca953x: clarify interrupt source detectionErnest Van Hoecke
There are multiple design tradeoffs and considerations in how the PCA953x driver detects the source(s) of an interrupt. This driver supports PCAL variants with input latching, a feature that is constrained by the fact that the interrupt status and input port registers cannot be read atomically. These limits and the design decisions deserve an in-depth explanation. Update the documentation to clarify these hardware limits and describe how the driver determines pending interrupts, and how it makes use of the PCAL input latching. Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20260107093125.4053468-1-ernestvanhoecke@gmail.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-01-08dt-bindings: soc: mediatek: dvfsrc: Document clockNicolas Frattaroli
The DVFSRC hardware has a clock on all platforms. Instead or proliferating the culture of omitting clock descriptions in the clock controller drivers or marking them critical instead of declaring these types of relationships, add this one to the binding. Any device that wishes to use this binding should figure out their incomplete or incorrect clock situation first before piling more features on top. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-08dt-bindings: ata: ahci-platform: Drop unnecessary select schemaRob Herring (Arm)
The "select" schema is not necessary. It looks like it is there to prevent matching on "generic-ahci" compatible, but that's not necessary because this is the only place "generic-ahci" compatible is present. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2026-01-08dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 boardRebecca Cran
Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) compatibles. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Tan Siewert <tan.siewert@hetzner.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251218161816.38155-2-rebecca@bsdio.com [arj: Drop erroneous Tested-by tag from Tan] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMCPeter Shen
This patch adds the compatible string for the Facebook Anacapa BMC which uses an Aspeed AST2600 SoC. This is required before adding the board's device tree source file. Signed-off-by: Peter Shen <sjg168@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> [arj: Insert provided Acked-by tag from Krzysztof, drop misspelled one] Link: https://lore.kernel.org/linux-aspeed/259e917f-0570-40d6-983f-bfe9d77444a7@kernel.org/ Link: https://patch.msgid.link/20251219091632.1598603-2-sjg168@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-07Documentation: hid: intel-ish-hid: Document PRODUCT_FAMILY firmware matchingVishnu Sankar
Document the ISH firmware filename matching rules, including the new PRODUCT_FAMILY-based patterns and their search order. This aligns the documentation with the driver behavior and provides clear guidance for vendors supplying custom ISH firmware. Signed-off-by: Vishnu Sankar <vishnuocv@gmail.com> Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.com>
2026-01-07thermal: int340x: processor_thermal: Enable slow workload type hintsSrinivas Pandruvada
On processors starting from Panther Lake, additional workload type hints are provided. The hardware analyzes workload residencies over an extended period to determine whether the workload classification tends toward idle/battery life states or sustained/performance states. Based on this long-term analysis, it classifies: Power Classification: If the workload exhibits more idle or battery life residencies, it is classified as "power". This is indicated by setting bit 4 of the current workload type. Performance Classification: If the workload exhibits more sustained or performance residencies, it is classified as "performance". This is indicated by clearing bit 4 of the current workload type. This approach enables applications to ignore short-term workload fluctuations and instead respond to longer-term power vs. performance trends. Hints of this type are called slow workload hints. To get notifications for slow workload hints, bit 22 in the thermal mailbox can be used for configuring workload interrupts. It is possible to exclusively enable slow workload hints or enable them in addition to the current workload hints. To enable slow workload hints, a new sysfs attribute is added to the existing workload hint attributes: workload_slow_hint_enable (RW): Write 1 to enable, 0 to disable. Reading this attribute shows the current state. This attribute is not present on any previous generation of processors. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> [ rjw: Dropped redundant local variables, changelog edits ] Link: https://patch.msgid.link/20251218222559.4110027-2-srinivas.pandruvada@linux.intel.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2026-01-07dt-bindings: i2c: atmel,at91sam: add microchip,lan9691-i2cRobert Marko
Document Microchip LAN969x I2C compatible. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20251229184004.571837-6-robert.marko@sartura.hr
2026-01-07dt-bindings: i2c: spacemit: add optional resetsEncrow Thorne
The I2C controller requires a reset to ensure it starts from a clean state. Add the 'resets' property to support this hardware requirement. Signed-off-by: Encrow Thorne <jyc0019@gmail.com> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com
2026-01-07Merge tag 'aspeed-6.20-devicetree-0' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt First batch of ASPEED Arm devicetree changes for 6.20 New platforms: - NVIDIA MSX4 BMC The NVIDIA MSX4 HPM (host platform module) is a reference board for managing up to 8 PCIe connected NVIDIA GPUs via ConnectX-8 (CX8) SuperNICs. The BMC manages all GPUs and CX8s for both telemetry and firmware update via MCTP over USB. The host CPUs are dual socket Intel Granite Rapids processors. For more detail on this architecture: https://developer.nvidia.com/blog/nvidia-connectx-8-supernics-advance-ai-platform-architecture-with-pcie-gen6-connectivity/ Updated platforms: - ast2600-evb (ASPEED): Various tidy-ups to address binding warnings - bletchley (Meta): Watchdog fix, tidy-ups to address binding warnings - clemente (Meta): HDD LED fix, GPIO line names, EEPROMs - harma (Meta): fanboard presence GPIO - santabarbara (Meta): IPMB, GPIO line names, additional IO expander * tag 'aspeed-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: ARM: dts: aspeed: bletchley: Fix ADC vref property names ARM: dts: aspeed: bletchley: Remove unused i2c13 property ARM: dts: aspeed: bletchley: Remove unused pca9539 properties ARM: dts: aspeed: bletchley: Fix SPI GPIO property names ARM: dts: aspeed: bletchley: Use generic node names ARM: dts: aspeed: g6: Drop clocks property from arm,armv7-timer ARM: dts: aspeed: ast2600-evb: Tidy up A0 work-around for UART5 ARM: dts: aspeed: g6: Drop unspecified aspeed,ast2600-udma node ARM: dts: aspeed: Drop syscon compatible from EDAC in g6 dtsi ARM: dts: aspeed: Use specified wp-inverted property for AST2600 EVB ARM: dts: aspeed: Remove sdhci-drive-type property from AST2600 EVB ARM: dts: aspeed: Add NVIDIA MSX4 HPM dt-bindings: arm: aspeed: Add NVIDIA MSX4 board ARM: dts: aspeed: clemente: move hdd_led to its own gpio-leds group ARM: dts: aspeed: clemente: add gpio line name to io expander ARM: dts: aspeed: santabarbara: Enable ipmb device for OCP debug card ARM: dts: aspeed: santabarbara: Add swb IO expander and gpio line names ARM: dts: aspeed: clemente: Add EEPROMs for boot and data drive FRUs ARM: dts: aspeed: harma: add fanboard presence sgpio ARM: dts: aspeed: bletchley: remove WDTRST1 assertion from wdt1 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Merge tag 'imx-fixes-6.19' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.19: - A mba8mx fix from Alexander Stein to correct Ethernet PHY IRQ trigger type - An i.MX95 fix from Carlos Song to correct I3C2 pclk - A couple of imx8qm-mek changes from Haibo Chen to fix light sensor interrupt type and usdhc2 regulator configuration - An imx6q-ba16 change from Ian Ray to fix RTC interrupt level - An imx8mp-dhcom-som change from Marek Vasut to fix sporadic Ethernet link bouncing caused by interruptions on the PHY reference clock - A couple of imx8mp-tx8p changes from Maud Spierings to fix compatible and eqos nvmem-cells - An ARM i.MX fix from Rob Herring to correct mc13xxx LED node names - An imx8qm-ss-dma change from Sherry Sun to correct DMA channels for LPUART - A couple of imx95-toradex-smarc changes from Vitor Soares to fix ethphy1 interrupt and SMARC_SDIO_WP label position * tag 'imx-fixes-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: mba8mx: Fix Ethernet PHY IRQ support arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells arm64: dts: freescale: moduline-display: fix compatible dt-bindings: arm: fsl: moduline-display: fix compatible ARM: dts: imx6q-ba16: fix RTC interrupt level arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt arm64: dts: add off-on-delay-us for usdhc2 regulator arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level ARM: dts: nxp: imx: Fix mc13xxx LED node names arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Documentation/process: maintainer-soc: Mark 'make' as commandsKrzysztof Kozlowski
Improve readability of the docs by marking 'make dtbs/dtbs_check' as shell commands. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://lore.kernel.org/r/20251223142726.73417-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Documentation/process: maintainer-soc: Be more explicit about defconfigKrzysztof Kozlowski
It is already documented but people still send noticeable amount of patches ignoring the rule - get_maintainers.pl does not work on arm64/configs/defconfig or any other shared ARM defconfig. Be more explicit, that one must not rely on typical/simple approach here for getting To/Cc list. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://lore.kernel.org/r/20251223142726.73417-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Merge branch '20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com' ↵Bjorn Andersson
into clk-for-6.20 Merge the Kaanapali camera, display, GPU, and video clock controller bindings through a topic branch, to allow making them available to the DeviceTree branch as well.
2026-01-07dt-bindings: clock: qcom: document the Kaanapali GPU Clock ControllerTaniya Das
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and Power domains (GDSC), but the requirement from the SW driver is to use the GDSC power domain from the clock controller to recover the GPU firmware in case of any failure/hangs. The rest of the resources of the clock controller are being used by the firmware of GPU. This module exposes the GDSC power domains which helps the recovery of Graphics subsystem. Add bindings documentation for the Kaanapali Graphics Clock and Graphics power domain Controller for Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-7-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add Kaanapali video clock controllerTaniya Das
Add device tree bindings for the video clock controller on Qualcomm Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-6-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add support for CAMCC for KaanapaliTaniya Das
Update the compatible and the bindings for CAMCC support on Kaanapali SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-5-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: document Kaanapali DISPCC clock controllerTaniya Das
Document device tree bindings for display clock controller for Qualcomm Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-4-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07Merge branch '20251202-sm8750_camcc-v1-2-b3f7ef6723f1@oss.qualcomm.com' into ↵Bjorn Andersson
clk-for-6.20 Merge the SM8750 camera clock controller binding through a topic branch, in order to allow the defines to made availabe to the DeviceTree branch as well.
2026-01-07dt-bindings: clock: qcom: Add camera clock controller for SM8750 SoCTaniya Das
Add device tree bindings for the camera clock controller on Qualcomm SM8750 platform. The camera clock controller is split between camcc and cambist. The cambist controls the mclks of the camera clock controller. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251202-sm8750_camcc-v1-2-b3f7ef6723f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add SDM439 Global Clock ControllerBarnabás Czémán
Add devicetree bindings for the global clock controller on Qualcomm SDM439 platform. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-3-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add MSM8940 Global Clock ControllerBarnabás Czémán
Add devicetree bindings for the global clock controller on Qualcomm MSM8940 platform. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-1-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: remoteproc: Add HSM M4F core on TI K3 SoCsBeleswar Padhi
Some of the TI K3 family of SoCs have a HSM (High Security Module) M4F core in the Wakeup Voltage Domain which could be used to run secure services like Authentication. Add the device tree bindings document for this HSM M4F core. The added example illustrates the DT node for the HSM core present on K3 J722S SoC. Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106104755.948086-2-b-padhi@ti.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2026-01-07dt-bindings: usb: qcom,dwc3: Correct MSM8994 interruptsKrzysztof Kozlowski
According to the reference manual, MSM8994 does have QUSB2 PHY and does not have DP/DM IRQs interrupts. It is also logical it has the same constraints as similar device: MSM8996. This fixes dtbs_check warnings like: msm8994-sony-xperia-kitakami-karin.dtb: usb@f92f8800 (qcom,msm8994-dwc3): interrupt-names:1: 'hs_phy_irq' was expected msm8994-sony-xperia-kitakami-karin.dtb: usb@f92f8800 (qcom,msm8994-dwc3): interrupt-names:2: 'dp_hs_phy_irq' was expected msm8994-sony-xperia-kitakami-karin.dtb: usb@f92f8800 (qcom,msm8994-dwc3): interrupt-names:3: 'dm_hs_phy_irq' was expected Fixes: 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding") Fixes: 6e762f7b8edc ("dt-bindings: usb: Introduce qcom,snps-dwc3") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260106185012.19551-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: usb: qcom,dwc3: Correct IPQ5018 interruptsKrzysztof Kozlowski
According to reference manual, IPQ5018 does not have QUSB2 PHY and its interrupts should rather match ones used in IPQ5332 (so power_event, eud_dmse_int_mx, eud_dpse_int_mx). Fixes: 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding") Fixes: 6e762f7b8edc ("dt-bindings: usb: Introduce qcom,snps-dwc3") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260106185012.19551-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: usb: Add Socionext Uniphier DWC3 controllerRob Herring (Arm)
The Socionext Uniphier DWC3 controller binding is already in use, but undocumented. It's a straight-forward binding similar to other DWC3 bindings. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://patch.msgid.link/20260105162418.2842825-1-robh@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: usb: Add Microchip LAN969x supportRobert Marko
Microchip LAN969x has DWC3 compatible controller, though limited to 2.0(HS) speed, so document it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229184004.571837-2-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07usb: gadget: f_sourcesink: Support maxburst configurability for bulk endpointsKrishna Kurapati
Add support to configure maxburst via configfs for bulk endpoints. Update gadget documentation describing the new configfs property. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://patch.msgid.link/20251227145224.2091397-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07Documentation/rtla: Document --bpf-action optionTomas Glozar
Add new option --bpf-action into common_timerlat_options.txt, including the format in which it takes the BPF program, and a reference to an example. Link: https://lore.kernel.org/r/20251126144205.331954-8-tglozar@redhat.com Signed-off-by: Tomas Glozar <tglozar@redhat.com>
2026-01-07Documentation/rtla: Rename sample/ to example/Tomas Glozar
The sample/ directory in tools/tracing/rtla was renamed to example/ in an earlier commit. Rename it also in the documentation. Reviewed-by: Wander Lairson Costa <wander@redhat.com> Link: https://lore.kernel.org/r/20251126144205.331954-7-tglozar@redhat.com Signed-off-by: Tomas Glozar <tglozar@redhat.com>
2026-01-07dt-bindings: pinctrl: sunxi: Allow pinmux sub-pattern with leading numbersChen-Yu Tsai
The pattern for pinmux node names is typically the peripheral name and instance number, followed by pingroup name if there are multiple options. Normally the instance number is directly appended to the peripheral name, like "mmc0" or "i2c2". But if the peripheral name ends with a number, then it becomes confusing. On the A20, the PS2 interface controller has two instances. This produces pinmux node names like "ps2-0-pins". Make the sub-pattern "[0-9]-" valid to fit this pattern. Avoid having to confusing "ps20-pins" name. Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-07dt-bindings: pinctrl: spacemit: add K3 SoC supportYixun Lan
Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares almost same logic with previous K1 generation, but has different register offset and pin configuration, for example the drive strength and schmitter trigger settings has been changed. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-07dt-bindings: pinctrl: spacemit: convert drive strength to schema formatYixun Lan
In order to better extend the pinctrl support for future new SoC, convert drive strength setting from free form text to more standard schema format. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-07dt-bindings: PCI: mediatek-gen3: Add MT7981 PCIe compatibleSjoerd Simons
Add compatible string for MediaTek MT7981 PCIe Gen3 controller. The MT7981 PCIe controller is compatible with the MT8192 PCIe controller. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251223-openwrt-one-network-v5-1-7d1864ea3ad5@collabora.com
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-14 19:40:31 +0000