summaryrefslogtreecommitdiff
path: root/Documentation
AgeCommit message (Collapse)Author
2025-12-17dt-bindings: eeprom: at24: Add compatible for Giantec GT24P64ALuca Weiss
Add the compatible for another 64Kb EEPROM from Giantec. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251210-fp4-cam-prep-v1-1-0eacbff271ec@fairphone.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2025-12-17dt-bindings: eeprom: at24: Add compatible for Belling BL24C04A/BL24C16FFUKAUMI Naoki
Add the compatible for Belling BL24C04A 4Kb EEPROM and BL24C16F 16Kb EEPROM. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251202084941.1785-2-naoki@radxa.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2025-12-16dt-bindings: arm: qcom: Add Medion SPRCHRGD deviceGeorg Gottleuber
Introduce new binding for the Medion SPRCHRGD 14 S1 notebook with X1E78100 SoC. Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204155212.230058-5-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-16dt-bindings: vendor-prefixes: Add Medion AGGeorg Gottleuber
Add Medion AG, a German electronics company, to the list of vendor prefixes. Link: https://www.medion.com/ Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204155212.230058-4-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-16dt-bindings: arm: qcom: Add TUXEDO Computers deviceGeorg Gottleuber
Introduce new binding for the TUXEDO Elite 14 Gen1 laptop with X1E78100 SoC. Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20251204155212.230058-3-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-16dt-bindings: vendor-prefixes: Add prefix for TUXEDO Computers GmbHGeorg Gottleuber
TUXEDO Computers GmbH is a German supplier for computers. Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251204155212.230058-2-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-17dt-bindings: i2c: qcom-cci: Document SM8750 compatibleHangxiang Ma
Add SM8750 compatible consistent with CAMSS CCI interfaces. Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251126-add-support-for-camss-on-sm8750-v1-1-646fee2eb720@oss.qualcomm.com Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
2025-12-17i2c: i801: Add support for Intel Nova Lake-SJarkko Nikula
Add SMBus PCI IDs on Intel Nova Lake-S. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20251124132816.470599-1-heikki.krogerus@linux.intel.com
2025-12-17dt-bindings: i2c: dw: Add Mobileye I2C controllersBenoît Monin
Add compatible string for the DesignWare-based I2C controllers present in Mobileye Eyeq6Lplus SoC, with a fallback to the default compatible. The same controllers are also present in the EyeQ7H, so add a compatible for those with a fallback to the Eyeq6Lplus compatible. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20251126-i2c-dw-v4-1-b0654598e7c5@bootlin.com
2025-12-16dt-bindings: cache: qcom,llcc: Document Glymur LLCC blockPankaj Patil
Document the Last Level Cache Controller on Glymur SoC Glymur LLCC has 12 base register regions and an additional AND, OR broadcast region, total 14 register regions Increase maxItems for reg and reg-names to allow 14 entries for Glymur Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251211-glymur_llcc_enablement-v3-1-43457b354b0d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-16dt-bindings: Updates Linus Walleij's mail addressLinus Walleij
My name is stamped into maintainership for a big slew of DT bindings. Now that it is changing, switch it over to my kernel.org mail address, which will hopefully be stable for the rest of my life. Signed-off-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20251216-maintainers-dt-v1-1-0b5ab102c9bb@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-16docs: dmaengine: add explanation for phys field in dma_async_tx_descriptor ↵Bhanu Seshu Kumar Valluri
structure Describe the need to initialize the phys field in the dma_async_tx_descriptor structure during its initialization. Signed-off-by: Bhanu Seshu Kumar Valluri <bhanuseshukumar@gmail.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> Link: https://patch.msgid.link/20251113064937.8735-1-bhanuseshukumar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dt-bindings: dma: rz-dmac: Document RZ/V2N SoC supportLad Prabhakar
Document the DMA controller on the Renesas RZ/V2N SoC, which is architecturally identical to the DMAC found on the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125212621.267397-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3UNiklas Söderlund
Document Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64 present in Renesas R-Car R8A779A0 V3U SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251106212342.2771579-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-16dt-bindings: clock: sprd,sc9860-clk: Allow "reg" for gate clocksRob Herring (Arm)
The gate bindings have an artificial split between a "syscon" and clock provider node. Allow "reg" properties so this split can be removed. Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com> Link: https://patch.msgid.link/20251029155615.1167903-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-16dt-bindings: display/ti: Simplify dma-coherent propertyKrzysztof Kozlowski
Common boolean properties need to be only allowed in the binding (":true"), because their type is already defined by core DT schema. Simplify dma-coherent property to match common syntax. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://patch.msgid.link/20251115122120.35315-4-krzk@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-16dt-bindings: display: simple: Add HannStar HSD156JUW2Renjun Wang
Add the HannStar HSD156JUW2 15.6" FHD (1920x1080) TFT LCD panel to the panel-simple compatible list. Signed-off-by: Renjun Wang <renjunw0@foxmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/tencent_8B5693A42B580AB3A5359849CCE23E67B407@qq.com
2025-12-16dt-bindings: panel: sw43408: adjust to reflect the DDIC and panel usedDavid Heidelberg
Add compatible for used LG panel. SW43408 is not panel, but DDIC. The panel itself is the LG LH546WF1-ED01, so introduce combined compatible for it. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251214-pixel-3-v7-2-b1c0cf6f224d@ixit.cz
2025-12-16dt-bindings: display: panel: document Samsung LTL106HL02 MIPI DSI panelSvyatoslav Ryhel
Samsung LTL106HL02 is a simple DSI which requires only a power supply and an optional reset gpio. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251110091440.5251-7-clamor95@gmail.com
2025-12-16dt-bindings: panel: s6e3fc2x01: Sort and remove unnecessary propertiesDavid Heidelberg
Properties are now sorted, reset-gpio and port property dropped because they are already accepted here as part of panel-common and usage of unevaluatedProperties. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106-dt-s6e3fc2x01-v2-1-deb87727152e@ixit.cz
2025-12-16dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2NLad Prabhakar
Add the compatible string "renesas,r9a09g057-mipi-dsi" for the Renesas RZ/V2H(P) (R9A09G057) SoC. While the MIPI DSI LINK registers are shared with the RZ/G2L SoC, the D-PHY register layout differs. Additionally, the RZ/V2H(P) uses only two resets compared to three on RZ/G2L, and requires five clocks instead of six. To reflect these hardware differences, update the binding schema to support the reduced clock and reset requirements for RZ/V2H(P). Since the RZ/V2N (R9A09G056) SoC integrates an identical DSI IP to RZ/V2H(P), the same "renesas,r9a09g057-mipi-dsi" compatible string is reused for RZ/V2N. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251015192611.241920-6-prabhakar.mahadev-lad.rj@bp.renesas.com
2025-12-16dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmuPeter Griffin
Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a "syscon" compatible") it is possible to register a regmap without the syscon compatible in the node. Update the bindings for google,gs101-pmu so that the syscon compatible is no longer required. As it isn't really correct to claim we are compatible with syscon (as a mmio regmap created by syscon will not work on gs101). Additionally (with the benefit of hindsight) PMU register writes were never working with a MMIO syscon on gs101, so the ABI break is justified. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251114-remove-pmu-syscon-compat-v2-1-9496e8c496c7@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-16dt-bindings: rng: add google,gs101-trng compatibleTudor Ambarus
Add support for the TRNG found on GS101. It works well with the current exynos850 TRNG support. The TRNG controller can be part of a power domain, allow the relevant property 'power-domains'. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251024-gs101-trng-v3-1-5d3403738f39@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-15dt-bindings: input: touchscreen: sitronix,st1232: Add Sitronix ST1624Rob Herring (Arm)
Add the Sitronix ST1624 which is compatible with ST1633. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251215212524.3318311-1-robh@kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2025-12-16f2fs: support large folio for immutable non-compressed caseJaegeuk Kim
This patch enables large folio for limited case where we can get the high-order memory allocation. It supports the encrypted and fsverity files, which are essential for Android environment. How to test: - dd if=/dev/zero of=/mnt/test/test bs=1G count=4 - f2fs_io setflags immutable /mnt/test/test - echo 3 > /proc/sys/vm/drop_caches : to reload inode with large folio - f2fs_io read 32 0 1024 mmap 0 0 /mnt/test/test Reviewed-by: Chao Yu <chao@kernel.org> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
2025-12-15dt-bindings: interrupt-controller: Document RZ/{T2H,N2H} ICUCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software interrupts and aggregate error interrupts. It has 16 software triggered interrupts (INTCPUn), 16 external pin interrupts (IRQn), a System error interrupt (SEI), two Cortex-A55 error interrupts (CA55_ERRn), two Cortex-R52 error interrupts for each of the two cores (CR52x_ERRn), two Peripheral error interrupts (PERI_ERRn), two DSMIF error interrupts (DSMIF_ERRn), and two ENCIF error interrupts (ENCIF_ERRn). The IRQn and SEI interrupts are exposed externally, while the others are software triggered. INTCPU0 to INTCPU13, IRQ 0 to IRQ13 are non-safety interrupts, while INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are exposed via a separate register space. Document them, and use RZ/T2H as a fallback for RZ/N2H as the ICU is entirely compatible. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251201112933.488801-2-cosmin-gabriel.tanislav.xa@renesas.com
2025-12-15dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoCLad Prabhakar
Document the Interrupt Control Unit (ICU) used on the Renesas RZ/V2N SoC. Although the ICU closely matches the design found on the RZ/V2H(P) family, it differs in its register layout, particularly in the reduced set of ECCRAM related registers. These variations require a distinct compatible string so that software can correctly match and handle the RZ/V2N implementation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251127162447.320971-2-prabhakar.mahadev-lad.rj@bp.renesas.com
2025-12-15dt-bindings: display: sitronix,st7920: Add DT schemaIker Pedrosa
Add binding for Sitronix ST7920 display. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Iker Pedrosa <ikerpedrosam@gmail.com> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patch.msgid.link/20251215-st7920-v7-1-36771009ec01@gmail.com
2025-12-15Documentation: admin-guide: blockdev: replace zone_capacity with ↵Yongpeng Yang
zone_capacity_mb when creating devices The "zone_capacity=%umb" option is no longer used. The effective option is now "zone_capacity_mb=%u", so update the documentation accordingly. Signed-off-by: Yongpeng Yang <yangyongpeng@xiaomi.com> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-12-15dt-bindings: samsung: exynos-pmu: Add compatible for ARTPEC-9 SoCSungMin Park
Add Axis ARTPEC-9 pmu compatible to the bindings documentation. It reuses the older samsung,exynos7-pmu design. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251029130731.51305-5-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-15dt-bindings: crypto: Document aspeed,ahbc property for Aspeed ACRYAndrew Jeffery
The g6 DTSI already provides the property and the driver errors out if the AHB controller's syscon can't be located, so define the property and mark it as required. Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://patch.msgid.link/20251211-dev-dt-warnings-all-v1-10-21b18b9ada77@codeconstruct.com.au Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-15dt-bindings: bus: aspeed: Require syscon for AST2600 AHB controllerAndrew Jeffery
The AST2600's ACRY (eliptic curve and RSA crypto engine) requires access to configuration exposed by the AHB controller. The devicetree already describes the AHB controller node as a syscon, so require this in the binding to satisfy the ACRY relationship. Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://patch.msgid.link/20251211-dev-dt-warnings-all-v1-9-21b18b9ada77@codeconstruct.com.au Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-15filelock: allow lease_managers to dictate what qualifies as a conflictJeff Layton
Requesting a delegation on a file from the userland fcntl() interface currently succeeds when there are conflicting opens present. This is because the lease handling code ignores conflicting opens for FL_LAYOUT and FL_DELEG leases. This was a hack put in place long ago, because nfsd already checks for conflicts in its own way. The kernel needs to perform this check for userland delegations the same way it is done for leases, however. Make this dependent on the lease_manager by adding a new ->lm_open_conflict() lease_manager operation and have generic_add_lease() call that instead of check_conflicting_open(). Morph check_conflicting_open() into a ->lm_open_conflict() op that is only called for userland leases/delegations. Set the ->lm_open_conflict() operations for nfsd to trivial functions that always return 0. Reviewed-by: Chuck Lever <chuck.lever@oracle.com> Signed-off-by: Jeff Layton <jlayton@kernel.org> Link: https://patch.msgid.link/20251204-dir-deleg-ro-v2-2-22d37f92ce2c@kernel.org Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-12-15spi: dt-bindings: st,stm32-spi: add 'power-domains' propertyAlain Volmat
STM32 SPI may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 SPI. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://patch.msgid.link/20251215-stm32-spi-mp2x-dt-updates-v1-1-464a5fd20f13@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-12-15dt-bindings: display: rockchip: dw-hdmi: Add compatible for RK3368 HDMIHeiko Stuebner
Define a new compatible for RK3368 HDMI. The RK3368 HDMI also uses a PHY internal to the controller, so works similar to other controllers, with the exception that the RK3368 only has one VOP, so there is no source selection needed. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251021074254.87065-2-heiko@sntech.de
2025-12-15fs: Remove internal old mount API codeEric Sandeen
Now that the last in-tree filesystem has been converted to the new mount API, remove all legacy mount API code designed to handle un-converted filesystems, and remove associated documentation as well. (The code to handle the legacy mount(2) syscall from userspace is still in place, of course.) Tested with an allmodconfig build on x86_64, and a sanity check of an old mount(2) syscall mount. Signed-off-by: Eric Sandeen <sandeen@redhat.com> Link: https://patch.msgid.link/20251212174403.2882183-1-sandeen@redhat.com Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-12-15init: remove deprecated "load_ramdisk" and "prompt_ramdisk" command line ↵Askar Safin
parameters ...which do nothing. They were deprecated (in documentation) in 6b99e6e6aa62 ("Documentation/admin-guide: blockdev/ramdisk: remove use of "rdev"") in 2020 and in kernel messages in c8376994c86c ("initrd: remove support for multiple floppies") in 2020. Signed-off-by: Askar Safin <safinaskar@gmail.com> Link: https://patch.msgid.link/20251119222407.3333257-2-safinaskar@gmail.com Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-12-15dt-bindings: display: sitronix,st7571: add example for SPIMarcus Folkesson
Add example for using st7571 with SPI. Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Link: https://patch.msgid.link/20251215-st7571-split-v3-7-d5f3205c3138@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-12-15PM: sleep: Do not flag runtime PM workqueue as freezableRafael J. Wysocki
Till now, the runtime PM workqueue has been flagged as freezable, so it does not process work items during system-wide PM transitions like system suspend and resume. The original reason to do that was to reduce the likelihood of runtime PM getting in the way of system-wide PM processing, but now it is mostly an optimization because (1) runtime suspend of devices is prevented by bumping up their runtime PM usage counters in device_prepare() and (2) device drivers are expected to disable runtime PM for the devices handled by them before they embark on system-wide PM activities that may change the state of the hardware or otherwise interfere with runtime PM. However, it prevents asynchronous runtime resume of devices from working during system-wide PM transitions, which is confusing because synchronous runtime resume is not prevented at the same time, and it also sometimes turns out to be problematic. For example, it has been reported that blk_queue_enter() may deadlock during a system suspend transition because of the pm_request_resume() usage in it [1]. It may also deadlock during a system resume transition in a similar way. That happens because the asynchronous runtime resume of the given device is not processed due to the freezing of the runtime PM workqueue. While it may be better to address this particular issue in the block layer, the very presence of it means that similar problems may be expected to occur elsewhere. For this reason, remove the WQ_FREEZABLE flag from the runtime PM workqueue and make device_suspend_late() use the generic variant of pm_runtime_disable() that will carry out runtime PM of the device synchronously if there is pending resume work for it. Also update the comment before the pm_runtime_disable() call in device_suspend_late(), to document the fact that the runtime PM should not be expected to work for the device until the end of device_resume_early(), and update the related documentation. This change may, even though it is not expected to, uncover some latent issues related to queuing up asynchronous runtime resume work items during system suspend or hibernation. However, they should be limited to the interference between runtime resume and system-wide PM callbacks in the cases when device drivers start to handle system-wide PM before disabling runtime PM as described above. Link: https://lore.kernel.org/linux-pm/20251126101636.205505-2-yang.yang@vivo.com/ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://patch.msgid.link/12794222.O9o76ZdvQC@rafael.j.wysocki
2025-12-15dt-bindings: mmc: sdhci-of-aspeed: Switch ref to sdhci-common.yamlAndrew Jeffery
Enable use of common SDHCI-related properties such as sdhci-caps-mask as found in the AST2600 EVB DTS. Cc: stable@vger.kernel.org # v6.2+ Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-12-15dt-bindings: clock: add Amlogic T7 peripherals clock controllerJian Hu
Add DT bindings for the peripheral clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251212022619.3072132-4-jian.hu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-12-15dt-bindings: clock: add Amlogic T7 PLL clock controllerJian Hu
Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20251212022619.3072132-2-jian.hu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-12-15Merge drm/drm-next into drm-misc-nextMaxime Ripard
Let's kickstart the v6.20 (7.0?) release cycle. Signed-off-by: Maxime Ripard <mripard@kernel.org>
2025-12-15dt-bindings: watchdog: xlnx,versal-wwdt: Add optional power-domains propertyHarini T
AMD/Xilinx Versal Window Watchdog Timer has its own power domain, so add an optional property to describe it. Signed-off-by: Harini T <harini.t@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20250130120233.742879-1-harini.t@amd.com
2025-12-15ata: libata: Add libata.force parameter max_secNiklas Cassel
Add a new libata.force parameter called max_sec. The parameter can take an arbitrary value using the format: libata.force=max_sec=<number of 512B sectors> e.g. libata.force=max_sec=8191 or libata.force=max_sec=2048 This will allow the user to set an arbitrary maximum command size (dev->max_sectors) using libata.force. We cannot remove the existing libata.force parameters "max_sec_128" and "max_sec_1024", as these are a part of the exising user facing API. Signed-off-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2025-12-14dt-bindings: remoteproc: Fix dead link to Keystone DSP GPIO bindingSoham Metha
The old text binding 'gpio-dsp-keystone.txt' was replaced by a DT schema in commit aff0a1701b020c8e6b172f28828fd4f3e6eed41a ("dt-bindings: gpio: Convert ti,keystone-dsp-gpio to DT schema"). Update the reference to point to the new file. Signed-off-by: Soham Metha <sohammetha01@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251203180337.50831-1-sohammetha01@gmail.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2025-12-14spi: dt-bindings: renesas,rzv2h-rspi: document optional support for DMACosmin Tanislav
The IP supports using DMA for reading and writing data from the FIFO, document it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251201134229.600817-11-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-12-14regulator: dt-bindings: Add MAX77675 regulatorJoan Na
Add device tree binding YAML schema for the Maxim MAX77675 PMIC regulator. Signed-off-by: Joan Na <joan.na@analog.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251207032907.4850-2-joan.na@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-12-14dt-bindings: arm: aspeed: Add NVIDIA MSX4 boardMarc Olberding
Adds a compatible string for NVIDIA's MSX4 BMC board. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Marc Olberding <molberding@nvidia.com> Link: https://patch.msgid.link/20251126-msx1_devicetree-v5-1-e508d13e2dda@nvidia.com [arj: Consistent capitalisation in subject, grammar] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-12-14Merge tag 'irq-urgent-2025-12-12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Ingo Molnar: - Fix error code in the irqchip/mchp-eic driver - Fix setup_percpu_irq() affinity assumptions - Remove the unused irq_domain_add_tree() function * tag 'irq-urgent-2025-12-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/mchp-eic: Fix error code in mchp_eic_domain_alloc() irqdomain: Delete irq_domain_add_tree() genirq: Allow NULL affinity for setup_percpu_irq()
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-15 10:42:21 +0000