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2026-07-21bpf, arm64: Optimize cast_user code generationPuranjay Mohan
cast_user converts an arena offset into a user address by combining the low 32 bits of the pointer with the upper 32 bits of user_vm_start, while keeping a NULL pointer NULL. The current sequence always emits six instructions: it materializes user_vm_start >> 32 into a register, shifts it into place, and ORs in the offset. The upper half of user_vm_start is a constant, so it can be written directly onto the offset with MOVK. Move the 32-bit offset into dst (which also zeroes the upper 32 bits), then MOVK the non-zero halfwords of the upper address, branching over the MOVKs when the offset is zero so NULL is preserved. This emits at most four instructions, and only one when the upper half of user_vm_start is zero. The generated code is equivalent. Before: ; bpf_addr_space_cast(page1, 1, 0); 7c: mov w10, w8 80: mov w8, #1 84: lsl x8, x8, #32 88: cbz x10, 0xffff800087b80c20 8c: orr x10, x8, x10 90: mov x8, x10 After: ; bpf_addr_space_cast(page1, 1, 0); 7c: mov w8, w8 80: cbz w8, 0xffff800087b80c28 84: movk x8, #1, lsl #32 Signed-off-by: Puranjay Mohan <puranjay@kernel.org> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/bpf/20260721105921.1070501-1-puranjay@kernel.org Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-07-21Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "RISC-V: - Avoid redundant allocations when allocating IMSIC page tables - Apply SBI FWFT LOCK flag only on successful set - Bound SBI PMU counter mask scan to BITS_PER_LONG, since on RV32 the PMU SBI start/stop helper can only access 32 PMU counters. - Skip TLB flush when G-stage PTE becomes valid if the Svvptc extension is available. - Always show Zicbo[m|z|p] block sizes in ONE_REG - Inject instruction access fault on unmapped guest fetch - Use raw spinlock for irqs_pending and irqs_pending_mask - Fix Spectre-v1 in vector register access via ONE_REG x86: - Fixes to SEV selftests - Once free_nested() did a VMCLEAR of shadow VMCS, there's no need to VMCLEAR it again if the kernel is preempted and thread migration happens - Preserve nested TDP shadow page tables if they are used as roots, instead of clearing them unnecessarily - Fix use of stale data if out-of-memory happens after vendor module reload - Check for invalid/obsolete root *after* making MMU pages available, because the latter can make a page invalid - Only reset TSC Deadline Timer in apic_timer_expired on KVM_RUN" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: Only reset TSC Deadline Timer in apic_timer_expired on KVM_RUN KVM: selftests: sev_init2_tests: Derive SEV availability from KVM KVM: selftests: sev_smoke_test: Only run VM types the host offers KVM: x86/mmu: Fix use-after-free on vendor module reload KVM: x86/mmu: Preserve nested TDP shadow page tables if they are used as roots KVM: x86: Check for invalid/obsolete root *after* making MMU pages available KVM: nVMX: Hide shadow VMCS right after VMCLEAR KVM: riscv: Fix Spectre-v1 in vector register access RISC-V: KVM: Serialize virtual interrupt pending state updates RISC-V: KVM: Inject instruction access fault on unmapped guest fetch RISC-V: KVM: Zicbo[m|z|p] block sizes should be always present in ONE_REG riscv: kvm: Skip TLB flush when G-stage PTE becomes valid with Svvptc KVM: riscv: PMU: Bound counter mask scan to BITS_PER_LONG KVM: riscv: SBI FWFT: Apply LOCK flag only on successful set RISC-V: KVM: Avoid redundant page-table allocations in ioremap topup
2026-07-21arm64/mm: Check the requested PFN range during memory removalRichard Cheng
prevent_memory_remove_notifier() advances pfn while scanning the requested range for early memory. When the loop completes, pfn is at or beyond end_pfn. Passing it to can_unmap_without_split() therefore checks a range after the one being offlined. Consequently, a valid request can be rejected based on the following range, while a request that would split a leaf mapping can be accepted if the shifted range can be unmapped without a split. This was observed with CXL DAX memory, where the final memory block was incorrectly allowed to be offlined. Pass arg->start_pfn into can_unmap_without_split() so it checks the requested range. Fixes: 95a58852b0e5 ("arm64/mm: Reject memory removal that splits a kernel leaf mapping") Signed-off-by: Richard Cheng <icheng@nvidia.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-21arm64: Correct value returned by ESR_ELx_FSC_ADDRSZ_nL()Steven Price
Address size fault, level -1 is encoded as 0b101001 or 0x29 according to the Arm ARM. Correct the value to match the spec. This also matches the offset of "level -1 address size fault" in the fault_info array in fault.c. Fixes: fb8a3eba9c81 ("KVM: arm64: Only read HPFAR_EL2 when value is architecturally valid") Signed-off-by: Steven Price <steven.price@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-21arm64: dts: mediatek: mt6359: use proper compatible for rtcLouis-Alexis Eyraud
The MT6359 PMIC include file uses directly "mediatek,mt6358-rtc" compatible string for the rtc subnode, but not its own compatible string. Now that the "mediatek,mt6359-rtc" compatible is properly declared in the dt-bindings, use it with "mediatek,mt6358-rtc" as fallback. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-07-21arm64: dts: mediatek: mt8395-radxa-nio-12l: Add MT6365 PMIC suppliesLouis-Alexis Eyraud
Radxa NIO-12L EVK board integrates a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board devicetree file. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-07-21arm64: dts: mediatek: mt8395-genio-common: Add MT6365 PMIC suppliesLouis-Alexis Eyraud
Mediatek Genio 1200 EVK board integrates a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board common definition include file. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-07-21arm64: dts: mediatek: mt8390-genio-common: Add MT6365 PMIC suppliesLouis-Alexis Eyraud
Mediatek Genio 510 and 700 EVK boards integrate a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board common definition include file. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-07-21Merge tag 'kvm-riscv-fixes-7.2-1' of https://github.com/kvm-riscv/linux into ↵Paolo Bonzini
HEAD KVM/riscv fixes for 7.2, take #1 - Avoid redundant page-table allocations in ioremap pcache topup - Apply SBI FWFT LOCK flag only on successful set - Bound SBI PMU counter mask scan to BITS_PER_LONG - Skip TLB flush when G-stage PTE becomes valid with Svvptc - Zicbo[m|z|p] block sizes should be always present in ONE_REG - Inject instruction access fault on unmapped guest fetch - Serialize virtual interrupt pending state updates using raw spinlock - Fix Spectre-v1 in vector register access via ONE_REG
2026-07-21KVM: x86: Only reset TSC Deadline Timer in apic_timer_expired on KVM_RUNVenkatesh Srinivas
On Intel platforms with a VMX preemption timer and APICv, if a VMM calls KVM_GET_LAPIC before KVM_GET_MSRS to save the vCPU state, it is possible to lose a pending timer interrupt. If the thread running these ioctls is migrated to another core after calling KVM_GET_LAPIC but before KVM_GET_MSRS and the guest is using their LAPIC timer in TSC-deadline mode, not only does the save LAPIC state not carry the pending interrupt, the TSCDEADLINE MSR will be zeroed. After migration across CPUs, KVM_GET_MSRS calls vcpu_load, posting the interrupt and clearing the MSR: vcpu_load() -> kvm_arch_vcpu_load() -> kvm_lapic_restart_hv_timer() -> start_hv_timer() -> apic_timer_expired() -> kvm_apic_inject_pending_timer_irqs() . post interrupt into the LAPIC state . clear IA32_TSCDEADLINE The saved LAPIC state will be missing the pending interrupt and the saved MSR will be zero. Oops. Fix by only posting an interrupt when we're attempting to enter the guest (vcpu->wants_to_run == true), not for vcpu_load from other paths. Assisted-by: gemini:gemini-3.1-pro-preview Debugged-by: David Matlack <dmatlack@google.com> Debugged-by: Sean Christopherson <seanjc@google.com> Debugged-by: Jim Mattson <jmattson@google.com> Debugged-by: James Houghton <jthoughton@google.com> Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org> Message-ID: <20260715234234.15382-2-venkateshs@chromium.org> Reviewed-by: James Houghton <jthoughton@google.com> Reviewed-by: Chao Gao <chao.gao@intel.com> Cc: stable@vger.kernel.org Fixes: ae95f566b3d2 ("KVM: X86: TSCDEADLINE MSR emulation fastpath", 2020-05-15) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-07-21KVM: x86/mmu: Fix use-after-free on vendor module reloadPhil Rosenthal
mmu_destroy_caches() destroys pte_list_desc_cache and mmu_page_header_cache, but leaves both pointers unchanged. The pointers live in kvm.ko, and therefore survive when a vendor module is unloaded while kvm.ko remains loaded. If creation of pte_list_desc_cache fails during a subsequent vendor module load, its assignment sets pte_list_desc_cache to NULL and the error path calls mmu_destroy_caches(). mmu_page_header_cache still points to the cache destroyed during the preceding vendor module unload. Passing that stale pointer to kmem_cache_destroy() causes a slab use-after-free. Reproduce the issue on a v7.1.3 kernel with CONFIG_KASAN=y, CONFIG_KASAN_GENERIC=y, CONFIG_KVM=m, and CONFIG_KVM_INTEL=m. A one-shot test hook forces pte_list_desc_cache to NULL on the second invocation of kvm_mmu_vendor_module_init(): 1. Load kvm.ko and kvm-intel.ko, creating both caches. 2. Unload only kvm_intel, leaving kvm.ko loaded. 3. Reload kvm_intel and force initialization through the -ENOMEM path. KASAN reports: BUG: KASAN: slab-use-after-free in kvm_mmu_vendor_module_init+0x5b/0x170 [kvm] ... kmem_cache_destroy+0x21/0x1d0 kvm_mmu_vendor_module_init+0x5b/0x170 [kvm] ... Allocated by task 16817: __kmem_cache_create_args+0x12c/0x3b0 __kmem_cache_create.constprop.0+0xb6/0xf0 [kvm] kvm_mmu_vendor_module_init+0x13b/0x170 [kvm] ... Freed by task 16820: kmem_cache_destroy+0x117/0x1d0 kvm_mmu_vendor_module_exit+0x21/0x30 [kvm] Clear both pointers immediately after destroying their caches so that the stored state reflects the caches' lifetime and repeated cleanup is safe. With the fix applied, the same injected vendor module reload fails with -ENOMEM as expected and produces no KASAN report. Fixes: cb498ea2ce1d ("KVM: Portability: Combine kvm_init and kvm_init_x86") Cc: stable@vger.kernel.org Signed-off-by: Phil Rosenthal <phil@phil.gs> Message-ID: <20260718-kvm-mmu-cache-uaf-v3-1-e103b93c74e1@phil.gs> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-07-21KVM: x86/mmu: Preserve nested TDP shadow page tables if they are used as rootsHyunwoo Kim
kvm_mmu_zap_oldest_mmu_pages() excludes a shadow page whose root_count is non-zero from top-level reclaim, because such a page cannot be freed. The path in mmu_page_zap_pte() that recursively zaps a parentless nested TDP child has no such check. As a result, a shadow page can be zapped even if the page itself can't be freed; as the comment in kvm_mmu_zap_oldest_mmu_pages() notes, zapping it will just force vCPUs to rebuild the page. As in top-level reclaim, do not recursively prepare zapping of a nested TDP child whose root_count is non-zero. Fixes: 2de4085cccea ("KVM: x86/MMU: Recursively zap nested TDP SPs when zapping last/only parent") Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-07-21KVM: x86: Check for invalid/obsolete root *after* making MMU pages availableSean Christopherson
Check for a "stale" page fault, i.e. for an invalid and/or obsolete root, after making MMU pages available for the shadow MMU. If reclaiming shadow pages zaps an in-use root, i.e. marks it invalid, then KVM will attempt to map memory into an invalid root. On its own, populating an invalid root is "fine", but because child shadow pages inherit their parent's role, any children created during the map/fetch will be created as invalid pages, thus violating KVM's invariant that invalid pages are never on the list of active MMU pages. Note, the underlying flaw has existed since KVM first started tracking invalid roots in 2008 (commit 2e53d63acba7, "KVM: MMU: ignore zapped root pagetables"), but the true badness only came along in 2020 (Linux 5.9) with the invariant that invalid shadow pages can't be on the list of active pages. Note #2, inheriting role.invalid when creating child shadow pages is also far from ideal; that flaw will be addressed separately. Reported-by: Hyunwoo Kim <imv4bel@gmail.com> Fixes: f95eec9bed76 ("KVM: x86/mmu: Don't put invalid SPs back on the list of active pages") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-07-21KVM: nVMX: Hide shadow VMCS right after VMCLEARHyunwoo Kim
free_nested() frees the shadow VMCS while vmcs01 still points to it. But because it is asynchronous with respect to loaded_vmcs_clear(), the vCPU might migrate before the pointer is cleared and __loaded_vmcs_clear() may then execute VMCLEAR. The VMCS needs to stay attached until its explicit VMCLEAR completes, but then it can be hidden and the page safely freed. Fixes: 355f4fb1405e ("kvm: nVMX: VMCLEAR an active shadow VMCS after last use") Cc: stable@vger.kernel.org Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-07-21KVM: arm64: vgic: Avoid double-deactivate of IRQs in the nested contextD Scott Phillips
In the nested state, the physical interrupt has already been deactivated through the HW bit in the LR. The extra deactivation would be harmless but can hit an errata case on AmpereOne, so avoid it here. On AmpereOne, deactivating a physical interrupt through ICC_DIR_EL1 or ICC_EOIR1_EL1 (depending on EOImode) which is not active, but is the highest priority pending interrupt causes the cpu to lose the interrupt pending state and also prevents the delivery of future interrupts. Fixes: 6dd333c8942b2 ("KVM: arm64: GICv3: nv: Plug L1 LR sync into deactivation primitive") Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-arm-kernel/20260710222128.416581-1-scott@os.amperecomputing.com/ Link: https://patch.msgid.link/20260714231158.496808-1-scott@os.amperecomputing.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-07-21arm64: versal-net: Switch Versal NET to firmware clock interfaceMichal Simek
Switch Versal NET from using fixed clocks to the firmware-based clock interface (versal-net-clk.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions. Add DT macro headers for Versal NET and base Versal clocks, power domains and mandatory resets required by the clock dtsi. Link: https://patch.msgid.link/77e6234f6cef3f78fb1c6c97142fa8055982e14e.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2026-07-20riscv: defconfig: thead: enable PCA953X GPIO driverMarek Szyprowski
Enable PCA953X GPIO driver to properly probe Wifi pwrseq driver on LicheePi4a board. Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Drew Fustini <fustini@kernel.org>
2026-07-20x86/msr: Document the I/O-like write semantics in the msr driverTim Wiederhake
Explain why msr_write() does not advance the index. [ bp: Massage commit message. ] Signed-off-by: Tim Wiederhake <twiederh@redhat.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260629173759.1770596-1-twiederh@redhat.com
2026-07-20Merge tag 'mm-hotfixes-stable-2026-07-20-11-37' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Pull misc fixes from Andrew Morton: "12 hotfixes. 8 are cc:stable and the remainder address post-7.1 issues or aren't considered appropriate for backporting. 10 are for MM. All are singletons - please see the relevant changelogs for details" * tag 'mm-hotfixes-stable-2026-07-20-11-37' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: mm/memory-failure: trace: change memory_failure_event to ras subsystem mm: page_reporting: allow driver to set batch capacity mm/kmemleak: fix checksum computation for per-cpu objects mm/damon/core: disallow overlapping input ranges for damon_set_regions() MAINTAINERS: add Usama as a THP reviewer fat: avoid stack overflow warning mm/damon/core: validate ranges in damon_set_regions() m68k: avoid -Wunused-but-set-parameter in clear_user_page() mm/huge_memory: set PG_has_hwpoisoned only after new folio head is established mm/page_vma_mapped: fix device-private PMD handling MAINTAINERS: s/SeongJae/SJ/ userfaultfd: prevent registration of special VMAs
2026-07-20x86/apic: Ensure ICR register write value is handled as 32 bitsMelody Wang
The low 32-bit ICR data is prepared by __prepare_ICR(), which returns a 32-bit value. However, when this value is assigned to a new variable, it's easy to mistakenly declare that variable with a different width. To avoid this class of mistakes, use __prepare_ICR() directly as the function argument instead of storing its result in an intermediate variable. This also shaves off a bunch of lines in the code. There should be no functionality change resulting from this. Signed-off-by: Melody Wang <huibo.wang@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260708012117.177959-1-huibo.wang@amd.com
2026-07-20entry, treewide: Make syscall_enter_from_user_mode[_work]() indicate syscall ↵Thomas Gleixner
execution The return values of syscall_enter_from_user_mode[_work]() are non-intuitive. Both functions return the syscall number which should be invoked by the architecture specific syscall entry code. The returned number can be: - the unmodified syscall number which was handed in by the caller - a modified syscall number (ptrace, seccomp, trace/probe/bpf) That has an additional twist. If the return value is -1L then the caller is not allowed to modify the return value as that indicates that the modifying entity requests to abort the syscall and set the return value already. That can obviously not be differentiated from a syscall which handed in -1 as syscall number. The most trivial way to deal with that is: set_return_value(regs, -ENOSYS); nr = syscall_enter_from_user_mode(regs, nr); if (valid(nr)) handle_syscall(regs, nr); That's what LOONGARCH, RISCV, and X86 do. But PowerPC and S390 do not preset the return value, so when user space hands in -1 and there is nothing setting the return value in the entry work code, then the syscall is skipped but the return value is whatever random data has been in the return value register. Change the return values of syscall_enter_from_user_mode[_work]() to boolean and return false, when either ptrace or seccomp request to skip the syscall. If they return true, update the syscall number as it might have been changed. That results in slightly different behaviour of the architectures versus tracing. If the syscall tracepoint has probe/BPF attached, those might set the syscall number to -1 and also set the return value. PowerPC and S390 will then overwrite that value with -ENOSYS. The other architectures will just ignore it like any other invalid syscall and use the modified one. Originally-by: Michal Suchánek <msuchanek@suse.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Tested-by: Michal Suchánek <msuchanek@suse.de> Link: https://patch.msgid.link/20260712141346.772209074@kernel.org
2026-07-20fscrypt: Always use blk-crypto for contents on block-based filesystemsEric Biggers
For encrypting and decrypting file contents on block-based filesystems (i.e., ext4 and f2fs, but not ceph and ubifs), always use blk-crypto instead of fs-layer crypto (direct use of crypto_skcipher). Since the blk-crypto API provides a fallback to CPU-based encryption, it's all that's needed on block-based filesystems. The support for two alternative block-based file contents encryption implementations, fs-layer and blk-crypto, existed mainly for historical reasons, as the fs-layer path came first. Some of it is also still needed for the non-block-based filesystems, but a lot of it isn't. Removing the duplicate fs-layer code paths greatly simplifies the code, most of which is done in later commits. Specific implementation details: - SB_INLINECRYPT now controls whether blk_crypto_config::allow_hw is set to true, instead of whether blk-crypto is used at all. The effect is that the semantics are preserved: the inlinecrypt mount option selects the use of inline encryption hardware instead of the CPU. - Set up a blk_crypto_key iff the file is a regular file on a block-based filesystem. To determine whether the filesystem is block-based, add a bit fscrypt_operations::is_block_based. - Remove fscrypt_select_encryption_impl(). Move the logging logic that was previously there into fscrypt_prepare_inline_crypt_key(). Note that blk_crypto_config_supported() is no longer needed. Reviewed-by: Christoph Hellwig <hch@lst.de> Link: https://patch.msgid.link/20260713023708.9245-6-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-07-20x86/bugs: Don't use cpu-type matching in cpu_vuln_blacklistPawan Gupta
Thomas Gleixner pointed out that cpu-type is a per-CPU property while hybrid is a system property; conflating the two in the CPU matching infrastructure is wrong. Currently, on a hybrid system x86_match_cpu() matches any cpu-type. This works if the intent is to find the possibility of a cpu-type in a system. But fails if matching for the cpu-type of a given CPU. Borislav posted a cleanup here: https://lore.kernel.org/all/20260703193222.GFakgORjvxwnZTPRnI@fat_crate.local To make way for the cleanup stop matching cpu-type in cpu_vuln_blacklist. RFDS is the only user, so drop the VULNBL_INTEL_TYPE entries and fold their RFDS bit into the base Alder Lake (0x97) and Raptor Lake (0xB7) blacklist entries. For now open-code cpu-type check in vulnerable_to_rfds(). In the future, if more vulnerabilities need cpu-type matching a helper can be added. No functional change intended. Fixes: 722fa0dba74f ("x86/rfds: Exclude P-only parts from the RFDS affected list") Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260708-cpu-type-vuln-v1-1-85c1d3c704db@linux.intel.com
2026-07-20arm64: dts: add devicetree for TQMa91xx on MBa93xxCAMarkus Niebel
This allows using TQMa91xxCA / TQMa91xxLA SoM on MBa93xxCA starter kit. While not having display all other interfaces of this mainboard can be used. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0Frank Li
The LPCG clock indices for ASRC0 and AUD_PLL_DIV0 are swapped. The ASRC0 LPCG provides only IMX_LPCG_CLK_4, so update the ASRC0 clock consumer to use IMX_LPCG_CLK_4 instead of the non-existent IMX_LPCG_CLK_0. Likewise, the AUD_PLL_DIV0 LPCG provides only IMX_LPCG_CLK_0, so update its clock consumer to use IMX_LPCG_CLK_0 instead of the non-existent IMX_LPCG_CLK_4. Fixes: 5125617c7a4d3 ("arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]") Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20arm64: dts: imx8qm-ss-lsio: add lsio mu8 and mu8bFrank Li
Add mu8 and mu8b mailbox nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20arm64: dts: imx8qm-ss-audio: add spdif1 nodeFrank Li
Add spdif1 and related lpcg node for imx8qm. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20arm64: dts: imx8qm-ss-dma: add lpuart4 nodeFrank Li
Add lpuart4 node for imx8qm. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: imx6ull-engicam-microgea: remove nand-ecc-strength and ↵Frank Li
nand-ecc-step-size The nand-ecc-strength and nand-ecc-step-size is bigger than 0. It doesn't make sense to set to 0. Remove it to fix below DTB_CHECKS warnings: arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): nand-ecc-strength: 0 is less than the minimum of 1 Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: imx6ul-isiot: remove undocument property clock-names of fsl,sgtl5000Frank Li
Remove undocument property clock-names of fsl,sgtl5000 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dtb: codec@a (fsl,sgtl5000): Unevaluated properties are not allowed ('clock-names' was unexpected) from schema $id: http://devicetree.org/schemas/sound/fsl,sgtl5000.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: imx53-smd: remove undocument property clock-names of ovti,ov5642Frank Li
Remove undocument properties ovti,ov5642 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx53-smd.dtb: ov5642@3c (ovti,ov5642): 'clock-names' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5642.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: imx6dl-plym2m: change #io-channel-cells to 1 of voltage dividerFrank Li
Change #io-channel-cells to 1 of voltage divider to fix below CHENCK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dtb: voltage-divider-vaccu (voltage-divider): #io-channel-cells: 1 was expected from schema $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: ls1021a-moxa-uc-8410a: remove undocument property default-state of ↵Frank Li
gpio-keys default-state = "on" is wrong copied from gpio-leds nodes. Remove it to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dtb: gpio-keys (gpio-keys): pushbtn-key: Unevaluated properties are not allowed ('default-state' was unexpected) from schema $id: http://devicetree.org/schemas/input/gpio-keys.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: ls1021a-moxa-uc-8410a: replace spansion,s25fl164k with jedec,spi-norFrank Li
spansion,s25fl164k (drivers/mtd/spi-nor/spansion.c) can be identified with the READ ID opcode (0x9F). Replace spansion,s25fl164k with jedec,spi-nor to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dtb: /soc/spi@1550000/flash@0: failed to match any schema with compatible: ['spansion,s25fl064l', 'spansion,s25fl164k'] So no other known DTB user this dts file and it is fine to broken potential back compatibility since spansion,s25fl164k already support by use jedec,spi-nor since 2015 commit 413780d7d7040 ("mtd: spi-nor: Add support for Spansion S25FL164K") Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: ls1021a-moxa-uc-8410a: use compatible string ↵Frank Li
ethernet-phy-ieee802.3-c22 Replace marvell,88e1118 with ethernet-phy-ieee802.3-c22. In drivers/net/mdio/of_mdio.c /* The following is a list of PHY compatible strings which appear in * some DTBs. The compatible string is never matched against a PHY * driver, so is pointless. We only expect devices which are not PHYs * to have a compatible string, so they can be matched to an MDIO * driver. Encourage users to upgrade their DT blobs to remove these. */ static const struct of_device_id whitelist_phys[] Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dtb: /soc/mdio@2d24000/ethernet-phy@0: failed to match any schema with compatible: ['marvell,88e1118'] No other known DTB user this dts file. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: ls1021a-twr: add power-supply for lcd panelFrank Li
Add power-supply for lcd panel to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-twr.dtb: panel (nec,nl4827hc19-05b): 'power-supply' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: ls1021a-moxa-uc-8410a: add led suffix to fix CHECK_DTBS warningsFrank Li
Add led suffix to fix below CHECK_DTBS warnings: ls1021a-moxa-uc-8410a.dtb: leds (gpio-leds): 'beeper', ... do not match any of the regexes: '(^led-[0-9a-f]$|led)', '^pinctrl-[0-9]+$' Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20ARM: dts: imx53-ard: change node name eim-cs1 to eim-cs1-busFrank Li
Change node name eim-cs1 to eim-cs1-bus to fix below CHECK_DTS warnings: arch/arm/boot/dts/nxp/imx/imx53-ard.dtb: eim-cs1@f4000000 (fsl,eim-bus): $nodename:0: 'eim-cs1@f4000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-20arm64: dts: mediatek: mt8192-asurada: Disable mmc1 on SpherionChen-Yu Tsai
Spherion does not have an micro SD card slot. Disable mmc1. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-07-20arm64: dts: amlogic: meson-axg-s400: enable mipi_pcie_analog_dphy for PCIeJun Yan
The PCIe PHY node references mipi_pcie_analog_dphy via its phys property. Enable this analog PHY node to make PCIe functionally viable. Fixes: 9715b01da6cf ("arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots") Signed-off-by: Jun Yan <jerrysteve1101@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20260624135650.727077-5-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-07-20arm64: dts: amlogic: meson-axg: Disable pcie_phy node by defaultJun Yan
Set the pcie_phy node to "disabled" as it is not used on some boards and should be enabled per-board when necessary. This change suppresses the deferred probe warning: platform ff644000.phy: deferred probe pending: (reason unknown) The meson-axg dtsi now disables pcie_phy by default, so enable it for the s400 board to support PCIe functionality. Signed-off-by: Jun Yan <jerrysteve1101@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20260624135650.727077-4-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-07-20arm64: dts: amlogic: meson-axg: Add missing nand_rb0 pin to nand_all_pinsJun Yan
The nand_all_pins pinctrl node was missing the nand_rb0 (ready/busy) pin description, which is required for NAND controller operation. Add it to the pinmux list. Fixes: be18d53c32b2 ("arm64: dts: amlogic: meson-axg: pinctrl node for NAND") Signed-off-by: Jun Yan <jerrysteve1101@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20260624135650.727077-3-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-07-20arm64: dts: amlogic: meson-axg: Disable nfc node by defaultJun Yan
nand_rb0 and emmc_ds share one pad. Before enabling nand_rb0 for nfc, disable nfc nodes by default to resolve pinctrl resource contention. No mainline AXG boards enable nfc currently thus no extra DTS adjustments are needed. Signed-off-by: Jun Yan <jerrysteve1101@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20260624135650.727077-2-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-07-20arm64: dts: amlogic: Correct indentation and whitespaceKrzysztof Kozlowski
Correct spaces or mix of tabs+spaces into proper tab-indented lines and remove other whitespace violations. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20260706093508.273968-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-07-20arm64: defconfig: Enable drivers for BeagleBadgeJudith Mendez
Enable drivers used on BeagleBadge[1]: - LED PWM Multicolor driver as a module - MCP SPI IO Expander driver as a module - Seven Segment display GPIO driver as module - Temperature Sensor driver as a module [1] https://www.beagleboard.org/boards/beaglebadge Signed-off-by: Judith Mendez <jm@ti.com> Link: https://www.beagleboard.org/boards/beaglebadge Link: https://patch.msgid.link/20260603192305.1347908-4-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-20Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netPaolo Abeni
Cross-merge networking fixes after downstream PR (net-7.2-rc4). No conflicts. Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2026-07-20arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entriesJun Guo
Describe the DMA-350 channel interrupt sources in DT using 8 interrupt entries, while all entries map to the same GIC SPI as wired on this platform. Signed-off-by: Jun Guo <jun.guo@cixtech.com> Link: https://lore.kernel.org/r/20260521072924.3000282-3-jun.guo@cixtech.com/ Signed-off-by: Gary Yang <gary.yang@cixtech.com>
2026-07-20m68k: coldfire: fix breakage of missed IO access updateGreg Ungerer
Fix the last remaining breakage caused by missing a SoC IO access update. Commit e1f3a00670d1 ("m68k: coldfire: use ColdFire specifc IO access in SoC code") missed this read16() call which should be mcf_read16(). Fixes: e1f3a00670d1 ("m68k: coldfire: use ColdFire specifc IO access in SoC code") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607180731.U4tiwFcQ-lkp@intel.com/ Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2026-07-19Merge tag 'riscv-for-linus-7.2-rc4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: - Call flush_cache_vmap() after populating new vmemmap pages, on all architectures. This avoids spurious faults on RISC-V microarchitectures that cache PTEs marked as non-present - Disable LTO for the vDSO to prevent the compiler from eliding functions that are used, but which don't appear to be - Fix an issue with libgcc's unwinder and signal handlers by dropping an unnecessary CFI landing pad instruction in __vdso_rt_sigreturn (similar to what was done on ARM64) - Avoid reading uninitialized memory under certain conditions in hwprobe_get_cpus() - Save some memory and I$ when CONFIG_DYNAMIC_FTRACE=n by avoiding our four-byte function alignment requirement in that case - Avoid clang warnings about null-pointer arithmetic in the I/O-port accessor macros (inb, outb, etc.) by ifdeffing them out when !CONFIG_HAS_IOPORT - Make the build of the lazy TLB flushing code in the vmalloc path depend on CONFIG_64BIT and CONFIG_MMU (since those platforms are the only ones that use it) * tag 'riscv-for-linus-7.2-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: hwprobe: Avoid uninitialized read in hwprobe_get_cpus() arch/riscv: vdso: remove CFI landing pad from rt_sigreturn riscv: vdso: Do not use LTO for the vDSO riscv: io: avoid null-pointer arithmetic in PIO helpers riscv: Gate FUNCTION_ALIGNMENT_4B on DYNAMIC_FTRACE mm/sparse-vmemmap: flush_cache_vmap() after hotplugging vmemmap riscv: mm: Make mark_new_valid_map() stuff depend on 64BIT && MMU
2026-07-19Merge tag 'x86-urgent-2026-07-19' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: - Reject too long acpi_rsdp= boot parameter values (Thorsten Blum) - Validate console=uart8250 baud rate to fix early boot hang (Thorsten Blum) - Remove dead Makefile rule (Ethan Nelson-Moore) * tag 'x86-urgent-2026-07-19' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/boot: Validate console=uart8250 baud rate to fix early boot hang x86/boot: Reject too long acpi_rsdp= values x86/cpu: Remove Makefile rule for removed UMC CPU support
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-22 05:27:45 +0000