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2026-07-15arm64: dts: qcom: kaanapali: Switch SCMI perf protocol to use power-domain-cellsMukesh Ojha
The SCMI protocol@13 (Performance Domain Management) node was using performance/power domain, not a clock. This was using the older mechanism for passing the SCMI performance domain index to scmi-cpufreq, which predates the #power-domain-cells support added in commit 92b2028b00ff ("cpufreq: scmi: Add support to parse domain-id using #power-domain-cells"). Switch to #power-domain-cells to match all other Qualcomm platforms (sm8750, glymur, hamoa) and align with the semantically correct representation. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260508082729.37674-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: kaanapali-qrd: Add PMIC Glink nodeKrishna Kurapati
Add PMIC Glink node on Kaanapali QRD Platform and add remote-endpoint linkages to DWC3 controller and QMP phy respectively. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260707-kaanapali-pmic-glink-v1-2-3f7d476672d9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: kaanapali-mtp: Add PMIC Glink nodeKrishna Kurapati
Add PMIC Glink node on Kaanapali MTP Platform and add remote-endpoint linkages to DWC3 controller and QMP phy respectively. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260707-kaanapali-pmic-glink-v1-1-3f7d476672d9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: kaanapali-mtp: Add SoCCP nodeJingyi Wang
Add SoCCP node on Kaanapali MTP board. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260709-knp-soccp-dt-v2-3-6e2bfca96088@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: kaanapali-qrd: Add SoCCP nodeJingyi Wang
Add SoCCP node on Kaanapali QRD board. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260709-knp-soccp-dt-v2-2-6e2bfca96088@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: kaanapali: Add SoCCP for Kaanapali SoCJingyi Wang
Add remoteproc PAS loader for SoCCP with its SMP2P. On Kaanapali, it is brought up by bootloader. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260709-knp-soccp-dt-v2-1-6e2bfca96088@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: milos: Add reset for sdhc_2Luca Weiss
Add the missing reset (BCR) for sdhc_2. Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260710-milos-sdhc2-reset-v1-1-c7a155a517ba@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: monaco-arduino-monza: add ina232 power sensorLoic Poulain
The Arduino Monza board has a TI INA232 current/power monitor connected on I2C12 at address 0x40. It is used to measure the board supply current through a 2 milliohms shunt resistor. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-3-e4375ce652d0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: x1-dell-thena: mark l12b and l15b always-onMichael Scott
The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Note that these supplies currently have no consumers described in mainline for dell-thena beyond the audio codec (vdd-buck/vdd-rxtx/ vdd-io on wcd938x), which can release them when the codec goes idle. The board-level gpio-fixed regulators that feed the Type-C retimer's VDDIO and other rails are not described with a vin-supply link, so the kernel cannot keep their parent LDOs alive on its own. This mirrors the same change Johan Hovold applied to every other X1E80100 board in a March 2025 series; commit 63169c07d740 ("arm64: dts: qcom: x1e80100-dell-xps13-9345: mark l12b and l15b always-on") is representative. The dell-thena board file was introduced four months later and did not inherit that change; this patch closes the gap. Fixes: e7733b42111c ("arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455") Cc: stable@vger.kernel.org Signed-off-by: Michael Scott <mike.scott@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Val Packett <val@packett.cool> Link: https://lore.kernel.org/r/20260521010935.1333494-4-mike.scott@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8250: correct frequencies in the Iris OPP tableDmitry Baryshkov
The OPP table for the Iris core is wrong, it copies the VDD table from the downstream kernel, but that table is written for the video_cc_mvs0_clk_src, while the upstream uses video_cc_mvs0_clk for OPP rate setting (which is clk_src divided by 3). Specify correct frequencies in the OPP table. Fixes: fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-iris-venus-fix-sm8250-v7-2-7bd2f0e5bae8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8250: sort out Iris power domainsDmitry Baryshkov
On SM8250 Iris core requires two power rails to function, MX (for PLLs) and MMCX (for everything else). The commit fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") added only MX power rail, but omitted MMCX voltage levels. Add MMCX domain to the Iris device node. Fixes: fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-iris-venus-fix-sm8250-v7-1-7bd2f0e5bae8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: qcom: ipq5018: Add GEPHY RX and TX clocksGeorge Moussalem
Add RX and TX clocks for the IPQ5018 GEPHY to enable the datapath. Fixes: f5f2b835e316 ("arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20260608-ipq5018-gephy-clocks-v4-3-fb2ccd56894b@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rateGeorge Moussalem
The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz. The CMN PLL driver did not account for the ref clock divider which is 2 for IPQ5018. Therefore, the computed rate was twice the actual output. With the driver now accounting for the CMN PLL reference clock divider (commit: 88c543fff756), set the correct reference clock rate. Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node") Signed-off-by: George Moussalem <george.moussalem@outlook.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260521-ipq5018-cmn-pll-rate-fix-v2-1-04b28a92e0f2@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Fix pm4125 vbus regulator compatible and constraintsRakesh Kota
Remove pm8150b fallback compatible from pm4125_vbus and fix regulator constraints in qrb2210 DTS files to use microvolt instead of microamp. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-4-999d78a87b81@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8450: Add missing PCM_OUT portEsteban Urrutia
An error in dmesg shows there is a mismatch between controller and DT dout-ports. Add PCM_OUT port to fix this. Signed-off-by: Esteban Urrutia <esteuwu@proton.me> Link: https://lore.kernel.org/r/20260622-sm8450-qol-v1-4-37e2ee8df9da@proton.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8750: enable ETR and CTCU devicesJie Gan
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-3-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: hamoa: enable ETR and CTCU devicesJie Gan
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device. The CTCU serves as the control unit for the ETR device, managing its behavior to determine how trace data is collected. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-2-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: glymur-crd: merge duplicate &pmh0101_gpios node extensionsGopikrishna Garmidi
The &pmh0101_gpios node is extended twice in glymur-crd.dtsi. The first extension defines the nvme_reg_en pinctrl state for the NVMe regulator enable GPIO (gpio14), and the second adds key_vol_up_default for the volume-up key (gpio6). Merge both pinctrl states into a single &pmh0101_gpios block to avoid the duplicate node extension. No functional change intended. Fixes: a5ad8a8e473c ("arm64: dts: qcom: Commonize Glymur CRD DTSI") Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260602-merge-duplicate-pmh0101-gpios-node-v2-1-251107b3d9fe@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: glymur: Add camera clock controller supportJagadeesh Kona
Add support for camera clock controller for camera clients to be able to request for camera clocks on Glymur SoC's. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624-glymur_camcc-v5-3-a321df74b1a1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: qcs6490: Add Vicharak Axon MiniAjit Singh
Add DTS for the Vicharak Axon Mini board based on the Qualcomm QCS6490 SoC. This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe support along with regulators. The UFS ICE block is kept disabled because enabling it currently causes an SError during qcom_ice_create() on this board. UFS works without ICE. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Ajit Singh <blfizzyy@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624125443.18729-4-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Enable first QUPv3 wrapper by defaultAbel Vesa
Since each serial engine will be enabled as needed in each board dts, there is no point of disabling the first QUPv3 wrapper in SoC dtsi. So enable it by default. This is also now in line with the other SoCs, and also with the second QUPv3 wrapper. Fixes: 844807e1f89d ("arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260709-dts-qcom-eliza-enable-qupv3-1st-v1-1-e9a6904d0dea@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add CPU and LLCC BWMONsAbel Vesa
Describe the CPU and LLCC bandwidth monitor nodes for Eliza, together with the corresponding OPP tables. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-dts-qcom-eliza-add-bwmon-v1-1-602a409f550f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Correct whitespace around '='Krzysztof Kozlowski
Coding convention asks that equal character '=' in property assignment is preceded and followed by a space. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-4-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Use lowercase hex for unit addresses and valuesKrzysztof Kozlowski
DTS coding style prefers lowercase hex. No functional change. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-3-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Use tab for indentationKrzysztof Kozlowski
Correct mix of tabs+spaces into proper tab indented lines. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-2-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Use hyphen in node namesKrzysztof Kozlowski
DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-1-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add Shikra EVK boardsKomal Bajaj
Add device trees for the Shikra EVK platform, which combines each of Shikra SoM variant with a common carrier board. Three EVK boards are introduced: - shikra-cqm-evk.dts: pairs with CQ2390M SoM (retail, with modem) - shikra-cqs-evk.dts: pairs with CQ2390S SoM (retail, without modem) - shikra-iqs-evk.dts: pairs with IQ2390S SoM (industrial, without modem) Also add shikra-evk.dtsi, it represents the common carrier-board and daughter-card configuration shared across all Shikra EVK variants. Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-5-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add Shikra IQ2390S SoM platformKomal Bajaj
Add device tree include for the IQ2390S variant of the Shikra System-on-Module, an industrial compute module integrating the Shikra SoC and PMIC for industrial IoT applications, designed to mount on carrier boards. - shikra-iqs-som.dtsi: Industrial SoM without modem (PM8150 PMIC) The DTSI includes the common shikra.dtsi and adds PM8150 PMIC regulator definitions specific to this variant. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-4-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add Shikra CQ2390M SoM platformKomal Bajaj
Add device tree include for the CQ2390M variant of the Shikra System-on-Module, a compact compute module integrating the Shikra SoC and PMIC for IoT applications, designed to mount on carrier boards. - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 and PM8005 PMIC) The DTSI includes the common shikra.dtsi, adds PM4125 and PM8005 PMIC peripheral definitions specific to this variant. Since PM8005 regulators are controlled by rpmpd, so disabling the pm8005 regulators. Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-3-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Introduce Shikra SoC base dtsiKomal Bajaj
Add initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform built around a heterogeneous CPU cluster (Cortex-A55 + Cortex-A78C) with RPM-based power and clock management. Enable support for the following peripherals: - CPU nodes - Global Clock Controller (GCC) - RPM-based clock controller (RPMCC) and power domains (RPMPD) - Interrupt controller - Top Level Mode Multiplexer (TLMM) - Debug UART - eMMC host controller - System timer and watchdog Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-2-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add HONOR MagicBook Art 14 device treeKonstantin Shabanov
Introduce support for the HONOR MagicBook Art 14 laptop. This version is based on the initial work by Kirill A. Korinsky [1] and Valentin Manea [2]. Supported: - Sound (with alsa-ucm-conf config [3]) - Speakers - Headphone jack - Bluetooth - Battery - HDMI - Touchpad - Keyboard (with backlight) - Touchscreen - WiFi - USB-C ports - USB-A port - UFS - H/W accel - DP over USB-C Untested: - Camera - Fingerprint reader - Sleep/Suspend Broken: - eDP [1]: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/ [2]: https://github.com/vamanea/linux-magicbook/blob/x1e80100-magicbook-6.19/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts [3]: https://github.com/alsa-project/alsa-ucm-conf/pull/755 Signed-off-by: Konstantin Shabanov <mail@etehtsea.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/ Link: https://github.com/vamanea/linux-magicbook/blob/x1e80100-magicbook-6.19/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts Link: https://github.com/alsa-project/alsa-ucm-conf/pull/755 Link: https://lore.kernel.org/r/20260629154812.9066-4-mail@etehtsea.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add PMIC nodes for CQS SoM and MTPAbel Vesa
Both the CQS SoM and the MTP have the following array of PMICs: PMK8550, PM7550, 2x PM8550VS, PMIV0102 and PMR735D. Since on Eliza there is already support for SPMI multi-master, it is necessary to duplicate the devicetree description for each of these PMICs, due to the SPMI bus index and address. So add a new Elize specific dtsi for each of these PMICs and include all of them in both the CQS SoM and MTP board dts. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-dts-qcom-eliza-mtp-evk-add-pmics-v1-1-f4f320f7c88b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add Eliza CQS EVK boardAbel Vesa
The Eliza CQS EVK board combines the CQ7790S-based (Eliza) SoM with the common Eliza EVK base board, which provides connectors for different peripherals. Add a common Eliza EVK dtsi for the base board bits that can be reused alongside other Eliza SoM variants. Then, add the final Eliza CQS EVK dts, including the CQS SoM and common EVK dtsi. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-3-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add Eliza CQS SoM platformAbel Vesa
The Eliza CQS (CQ7790S) System-on-Module is designed to be connected to an Eliza EVK base board. The SoM provides the SoC, PMICs, LPDDR and eMMC, while the EVK base board provides connectors for a multitude of peripherals. Add the Eliza CQS SoM DTSI so it can be included by the EVK board DTS. Describe the regulators and board clocks, enable eMMC support through SDHC1, specify the ADSP firmware and enable the ADSP remoteproc. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-2-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sc8280xp-x13s: Use predefined MCLK pinctrlPengyu Luo
Now that the predefined MCLK pinctrl configuration is available in the sc8280xp SoC DTSI, switch the ThinkPad X13s to use it. Drop the local, duplicate MCLK pin definition from the camera pinctrl node. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629065905.15651-4-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sc8280xp: Add camera MCLK pinctrlPengyu Luo
Define pinctrl definitions to enable camera master clocks on sc8280xp. Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Link: https://lore.kernel.org/r/20260629065905.15651-3-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sc8280xp-x13s: Fix the drive-strength of mclk pinPengyu Luo
The value can be retrieve via windbg on Windows. lkd> !dd f111000 L8 ctl_reg => 0x284 in drivers/pinctrl/qcom/pinctrl-msm.c function msm_gpio_dbg_show_one() ... drive = (ctl_reg >> g->drv_bit) & 7; // (0x284 >> 6) & 7 == 2 ... seq_printf(s, " %dmA", msm_regval_to_drive(drive)); // (drive + 1) * 2 == 6; ... So the value is 6, not 16, it matches Windows now. Fixes: 21927e94caa5 ("arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor") Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629065905.15651-2-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: talos: Add memory-region for audio PDEkansh Gupta
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629-talos-remoteheap-v3-1-4e23366c9196@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: glymur: Add label properties to CoreSight devicesJie Gan
Add label properties to TPDM and CTI nodes in the glymur device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: msm8996-xiaomi-gemini: Fix up ti,drv2604 enable GPIOKonrad Dybcio
Update the 'enable-gpio' property name to 'enable-gpios' to conform to the bindings for the TI DRV2604 haptics module. While at it, use the GPIO_ACTIVE_HIGH define instead of the raw literal. Fixes: 4ac46b3682c5 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260625-topic-ti_drv2604_dtwarn-v1-1-76e91fcafbe8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: lemans-evk: Describe the PCIe M.2 Key E connectorWei Deng
The lemans EVK has the PCIe M.2 Mechanical Key E connector to connect wireless connectivity cards over PCIe and UART interfaces. Hence, describe the connector node and link it with the PCIe 0 Root Port and UART17 nodes through graph port/endpoint. The M.2 Key E connector is powered by a 3.3V fixed regulator (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail (vreg_dcin_12v). Both regulators are always-on and are required by the pcie-m2-e-connector binding. Also add the serial1 = &uart17 alias, which is required for the Bluetooth serdev device to be enumerated on the UART17 interface. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260622-v3-lemans-split-v3-2-d26bb22594e3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: lemans: Add compatible to the PCIe Root PortWei Deng
Add 'compatible = "pciclass,0604"' to the pcieport0 node in lemans.dtsi to allow the PCI subsystem to associate the DT node with the PCI-to-PCI bridge device. This is required for downstream DT nodes (such as M.2 connectors described as graph endpoints of the Root Port) to be matched to PCI devices. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260622-v3-lemans-split-v3-1-d26bb22594e3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15x86/mm/pat: Take cpa_lock around large-page collapseDenis V. Lunev
Loading and unloading modules concurrently on several CPUs on a KASAN build, with a short delay injected at the CPA page-table lookup to widen the window, faults within minutes: BUG: KASAN: use-after-free in __change_page_attr+0x7cc/0x7e0 Write of size 8 at addr ffff888181139718 by task modprobe ... The buggy address belongs to the physical page: pfn:0x181139 ... page_type: f2(table) cpa_collapse_large_pages() rebuilds a leaf PMD from its 4K PTEs and frees the old PTE-table pages, while __change_page_attr() fetches a PTE pointer from a lockless lookup_address_in_pgd_attr() and writes it with set_pte_atomic() only later. When module text is served from a shared large ROX mapping the two run on the same PMD: CPU A (module load) CPU B (module finalize) ------------------- ----------------------- execmem_make_temp_rw set_memory_nx __change_page_attr split 2M -> 4K table P kpte = &P[i] (lockless) execmem_restore_rox set_memory_rox (CPA_COLLAPSE) cpa_collapse_large_pages rebuild leaf PMD flush_tlb_all pagetable_free(P) set_pte_atomic(kpte, ...) -> writes into freed P P is a page-table page (page_type: table), reused at once, so the write corrupts whatever got the page next: a bad-pte or bad-page splat, or a fatal fault once P has been turned into read-only text. The flush_tlb_all() before the free does not close this: its IPI only serializes against page-table walkers that run with interrupts off (e.g. GUP-fast); the walk in __change_page_attr() runs with interrupts on, so nothing stops it from holding a stale pointer into P. Serialize the collapse - the PMD rebuild, TLB flush and PTE-table free - under cpa_lock, the same lock __change_page_attr() now takes unconditionally since commit ("x86/mm/pat: stop gating cpa_lock on debug_pagealloc_enabled()"), so a concurrent walker can no longer hold a pointer into a table the collapse is about to free. Fixes: 41d88484c71c ("x86/mm/pat: restore large ROX pages after fragmentation") Signed-off-by: Denis V. Lunev <den@openvz.org> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Kiryl Shutsemau (Meta) <kas@kernel.org> Link: https://patch.msgid.link/20260715183453.2381141-1-den@openvz.org
2026-07-15riscv: hwprobe: Avoid uninitialized read in hwprobe_get_cpus()Mark Harris
When cpusetsize < cpumask_size(), hwprobe_get_cpus() did not fully initialize its copy of the cpu mask, which could cause non-deterministic results from the riscv_hwprobe syscall on a system with more than 8 CPUs when the supplied cpu mask is empty. Address this by fully initializing the cpu mask. Fixes: e178bf146e4b ("RISC-V: hwprobe: Introduce which-cpus flag") Signed-off-by: Mark Harris <mark.hsj@gmail.com> Reviewed-by: Nam Cao <namcao@linutronix.de> Reviewed-by: Michael Ellerman <mpe@kernel.org> Link: https://patch.msgid.link/20260714003056.73707-1-mark.hsj@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-07-15s390/perf_cpum_cf: Add missing array_index_nospec() to __hw_perf_event_init()Sumanth Korikkar
ev variable is userspace controlled via event->attr.config and used as an array index after bounds checking, but without speculation barriers. Add the missing array_index_nospec() call to prevent speculative execution. Cc: stable@vger.kernel.org Fixes: 212188a596d1 ("[S390] perf: add support for s390x CPU counters") Signed-off-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Thomas Richter <tmricht@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2026-07-15s390/checksum: Fix csum_partial() without vector facilityVasily Gorbik
Currently csum_partial() calls csum_copy() with copy=false and dst=NULL. On machines without the vector facility, csum_copy() falls back to cksm(dst, ...), causing the checksum to be calculated from address zero instead of the source buffer. The VX implementation already checksums data loaded from src. Make the fallback do the same by passing src to cksm(). Fixes: dcd3e1de9d17 ("s390/checksum: provide csum_partial_copy_nocheck()") Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2026-07-15x86/mm/pat: Don't gate cpa_lock on debug_pagealloc_enabled()Mike Rapoport (Microsoft)
The splitting and merging of kernel page table mappings between small and large is protected by cpa_lock. The merging is relatively new but the splitting is ancient. The splitting has a locking optimization: since DEBUG_PAGEALLOC forces all mappings to 4k, there are no large pages to split. So the code that *might* cause a split can just skip the locking (and a few other things). This is entertaining, but it adds complexity and makes for weird locking rules. Plus it's all for a debugging feature which makes the kernel super slow in the first place. Optimizing something which is already super slow and not used in production is not the best way to spend our complexity budget. Stop gating cpa_lock on debug_pagealloc_enabled() to simplify the code and the locking rules. [ dhansen: flesh out changelog ] Suggested-by: Dave Hansen <dave.hansen@intel.com> Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://patch.msgid.link/20260715144519.934289-1-rppt@kernel.org Link: https://lore.kernel.org/all/aab44f08-89f8-47fe-bee4-0ab6b25968c6@intel.com/
2026-07-15irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaroundMarek Vasut
Renesas R-Car S4/V4H/V4M GIC600 integration has address width for AXI or APB interface configured to 32 bit, it can therefore access only the first 4 GiB of physical address space. This information comes from R-Car V4H Interface Specification sheet; there is currently no technical update number assigned to this limitation. Further input from hardware engineer indicates that this limitation also applies to R-Car S4 and V4M. Name the limitation GEN4GICITS1, and add a driver quirk to mitigate this limitation. The quirk is keyed on the combination of the GIC implementation and the platform identification in the device tree. Co-developed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260707203743.88299-5-marek.vasut+renesas@mailbox.org
2026-07-15calibrate: Rework delay timer calibrationThomas Gleixner
The header define in asm/timex,h and the naming of the function to read the delay timer are confusing at best. Convert it to a config switch selected by the archictures which provide the functionality and rename the function to delay_read_timer(), which makes the purpose clear. Move the declaration to linux/delay.h where it belongs. Remove the resulting empty asm/timex.h files as well. No functional change. Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260410120317.978403520@kernel.org
2026-07-15treewide: Remove CLOCK_TICK_RATEThomas Gleixner
This has been scheduled for removal more than a decade ago and the comments related to it have been dutifully ignored. The last dependencies are gone. Remove it along with various now empty asm/timex.h files. Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://patch.msgid.link/20260410120317.910770161@kernel.org
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-22 16:19:06 +0000