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2026-04-06LoongArch: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrievalChengwen Feng
As a step towards unifying the interface for retrieving ACPI CPU UID across architectures, introduce a new function acpi_get_cpu_uid() for loongarch. While at it, add input validation to make the code more robust. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260401081640.26875-3-fengchengwen@huawei.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2026-04-06arm64: acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrievalChengwen Feng
As a step towards unifying the interface for retrieving ACPI CPU UID across architectures, introduce a new function acpi_get_cpu_uid() for arm64. While at it, add input validation to make the code more robust. Reimplement get_cpu_for_acpi_id() based on acpi_get_cpu_uid() for consistency, and move its implementation next to the new function for code coherence. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://patch.msgid.link/20260401081640.26875-2-fengchengwen@huawei.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2026-04-06hwspinlock: u8500: delete driverWolfram Sang
The U8500 platform was converted to DT around 2013 and is DT only meanwhile. This driver has never been converted to a DT driver, so it clearly hasn't been used since then. To ease upcoming refactoring in the hwspinlock subsystem, remove this obsolete driver. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20260401071141.4718-2-wsa+renesas@sang-engineering.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-06MIPS: dts: loongson64g-package: Switch to Loongson UART driverRong Zhang
Loongson64g is Loongson 3A4000, whose UART controller is compatible with Loongson 2K1500, which is NS16550A-compatible with an additional fractional frequency divisor register. Update the compatible strings to reflect this, so that 3A4000 can benefit from the fractional frequency divisor provided by loongson-uart. This is required on some devices, otherwise their UART can't work at some high baud rates, e.g., 115200. Tested on Loongson-LS3A4000-7A1000-NUC-SE with a 25MHz UART clock. Without fractional frequency divisor, the actual baud rate was 111607 (25MHz / 16 / 14, measured value: 111545) and some USB-to-UART converters couldn't work with it at all. With fractional frequency divisor, the measured baud rate becomes 115207, which is quite accurate. Signed-off-by: Rong Zhang <rongrong@oss.cipunited.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06mips: pci-mt7620: rework initialization procedureShiji Yang
Move the reset operation to the common part to reduce the code redundancy. They are actually the same and needed for all SoCs. Disabling power and clock are unnecessary for MT7620 and will be removed. In vendor SDK, it's used to save the power when the PCI driver is not selected. The MT7628 GPIO pinctrl has been removed because this should be done in device-tree. Some delay intervals have also been increased to follow the recommendations of the SoC SDK and datasheet. Tested on both MT7620 and MT7628. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06mips: pci-mt7620: add more register init valuesShiji Yang
These missing register init values are ported from the vendor SDK. It should have some stability enhancements. Tested on both MT7620 and MT7628. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06mips: pci-mt7620: fix bridge register accessShiji Yang
Host bridge registers and PCI RC control registers have different memory base. pcie_m32() is used to write the RC control registers instead of bridge registers. This patch introduces bridge_m32() and use it to operate bridge registers to fix the access issue. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06mips: dts: Add PCIe to EcoNet EN751221Caleb James DeLisle
Add PCIe based on EN7528 PCIe driver, also add two MT76 wifi devices to SmartFiber XP8421-B. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYsThéo Lebrun
The Mobileye EyeQ5 eval board (EPM) embeds two MDIO PHYs. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllersThéo Lebrun
Add both MACB/GEM instances found in the Mobileye EyeQ5 SoC. Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06MIPS: DEC: Rate-limit memory errors for non-KN01 parity systemsMaciej W. Rozycki
Similarly to memory errors in ECC systems also rate-limit memory parity errors for KN02-BA, KN02-CA, KN04-BA, KN04-CA DECstation and DECsystem models. Unlike with ECC these events are always fatal and are less likely to cause a message flood, but handle them the same way for consistency. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06MIPS: DEC: Rate-limit memory errors for KN01 systemsMaciej W. Rozycki
Similarly to memory errors in ECC systems also rate-limit memory parity errors for KN01 DECstation and DECsystem models. Unlike with ECC these events are always fatal and are less likely to cause a message flood, but handle them the same way for consistency. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06MIPS: DEC: Rate-limit memory errors for ECC systemsMaciej W. Rozycki
Prevent the system from becoming unusable due to a flood of memory error messages with DECstation and DECsystem models using ECC, that is KN02, KN03 and KN05 systems. It seems common for gradual oxidation of memory module contacts to cause memory errors to eventually develop and while ECC takes care of correcting them and the system affected can continue operating normally until the contacts have been cleaned, the unlimited messages make the system spend all its time on producing them, therefore preventing it from being used. Rate-limiting removes the load from the system and enables its normal operation, e.g.: Bus error interrupt: CPU memory read ECC error at 0x139cfb04 ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU partial memory write ECC error at 0x138c1f5c ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU partial memory write ECC error at 0x138c1f6c ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x139cff64 ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x136af00c ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x136af044 ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x136af0cc ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x136af0cc ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x136af0e4 ECC syndrome 0x54 -- corrected single bit error at data bit D3 Bus error interrupt: CPU memory read ECC error at 0x136af104 ECC syndrome 0x54 -- corrected single bit error at data bit D3 dec_ecc_be_backend: 34455 callbacks suppressed Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06MIPS: kernel: Remove $0 clobber from `mult_sh_align_mod'Maciej W. Rozycki
Remove rubbish $0 clobber added to inline asm within `mult_sh_align_mod' with the removal of support for GCC versions below 3.4 made with commit 57810ecb581a ("MIPS: Remove GCC_IMM_ASM & GCC_REG_ACCUM macros"). Previously a macro was used that, depending on GCC version, expanded to either `accum' or $0. Since the latter choice was only a placeholder to keep the syntax consistent and the register referred is hardwired, there is no point in having it here as it has no effect on code generation. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06arch/mips: Drop CONFIG_FIRMWARE_EDID from defconfig filesThomas Zimmermann
CONFIG_FIRMWARE_EDID=y depends on X86 or EFI_GENERIC_STUB. Neither is true here, so drop the lines from the defconfig files. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-06RISC-V: KVM: Fix shift-out-of-bounds in make_xfence_request()Jiakai Xu
The make_xfence_request() function uses a shift operation to check if a vCPU is in the hart mask: if (!(hmask & (1UL << (vcpu->vcpu_id - hbase)))) However, when the difference between vcpu_id and hbase is >= BITS_PER_LONG, the shift operation causes undefined behavior. This was detected by UBSAN: UBSAN: shift-out-of-bounds in arch/riscv/kvm/tlb.c:343:23 shift exponent 256 is too large for 64-bit type 'long unsigned int' Fix this by adding a bounds check before the shift operation. This bug was found by fuzzing the KVM RISC-V interface. Fixes: 13acfec2dbcc ("RISC-V: KVM: Add remote HFENCE functions based on VCPU requests") Signed-off-by: Jiakai Xu <jiakaiPeanut@gmail.com> Signed-off-by: Jiakai Xu <xujiakai2025@iscas.ac.cn> Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260403232011.2394966-1-xujiakai2025@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-05ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boardsMarek Vasut
Add DT overlays to support DH i.MX6 DHCOM SoM carrier board expansion modules. The following DT overlays are implemented: - PDK2: - DH 497-200 Display board in edge connector X12 - DH 505-200 Display board in edge connector X12 - DH 531-100 SPI/I2C board in header X21 - DH 531-200 SPI/I2C board in header X22 - DH 560-200 Display board in edge connector X12 - PicoITX: - DH 626-100 Display board in edge connector X2 Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdifFrank Li
The i.MX6SX LCDIF is not fully compatible with the i.MX28 LCDIF. The i.MX6SX controller provides additional overlay registers (AS_CTRL) which are not present on i.MX28. Linux has supported the dedicated compatible string since commit 45d59d704080 ("drm: Add new driver for MXSFB controller"). Other known DT users such as U-Boot and Barebox already support "fsl,imx6sx-lcdif", so removing the fallback compatible string is low risk since this device is used for display output only. Fix the following CHECK_DTB warning: /arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: lcdif@2220000 (fsl,imx6sx-lcdif): compatible: 'oneOf' conditional failed, one must be fixed: ['fsl,imx6sx-lcdif', 'fsl,imx28-lcdif'] is too long Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx25: rename node name tcq to touchscreenFrank Li
Rename node name tcq to touchscreen to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dtb: tscadc@50030000 (fsl,imx25-tsadc): 'tcq@50030400' does not match any of the regexes: '^adc@[0-9a-f]+$', '^pinctrl-[0-9]+$', '^touchscreen@[0-9a-f]+$' from schema $id: http://devicetree.org/schemas/mfd/fsl,imx25-tsadc.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: b850v3: Disable unused usdhc4Ian Ray
Disable the unused interface, to fix print an error message during boot: mmc3: Failed to initialize a non-removable card Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: b850v3: Define GPIO line namesIan Ray
Define GPIO line names for gpio4. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: b850v3: Use alphabetical sortingIan Ray
Use alphabetical sorting of references modification. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warningIan Ray
Set `phy-mode' on network switch CPU ports to eliminate a warning: mv88e6085 gpio-0:00: OF node /mdio-gpio/switch@0/ports/port@4 of CPU port 4 lacks the required "phy-mode" property Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100MbpsIan Ray
Configure maximum speed for the switch PHYs according to the electrical connections from PHY to RJ45 connector. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx7ulp: Add CPU clock and OPP table supportPeng Fan
Add missing CPU clock definitions and operating-points-v2 table for the Cortex-A7 on i.MX7ULP to enable proper CPU frequency scaling and integration with the cpufreq/OPP frameworks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx7-mba7: Deassert BOOT_EN after bootAlexander Feilke
Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals. Signed-off-by: Alexander Feilke <Alexander.Feilke@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: tqma7: add boot phase propertiesAlexander Feilke
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. Adds boot phase properties to essential resources in tqma7 device trees. This includes UART, SD-Card, eMMC and QSPI. Signed-off-by: Alexander Feilke <Alexander.Feilke@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx7s: add boot phase propertiesAlexander Feilke
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. Adds boot phase properties to essential resources in imx7s device trees. This includes the buses aips1-3, iomuxc and SOC access. Signed-off-by: Alexander Feilke <Alexander.Feilke@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: tqma6ul[l]: correct spelling of TQ-SystemsMax Merchel
TQ-Systems is written with a hyphen. Correct the spelling. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: mba6ulx: add boot phase propertiesMax Merchel
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. MBa6ULx need regulator, SD-Card, UART and watchdog access during boot process. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase propertiesMax Merchel
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. TQMa6UL need eMMC, I2C, GPIO and QSPI access during boot process. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6ul/imx6ull: add boot phase propertiesMax Merchel
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. All SoCs require buses (aips and spba), clock, iomuxc and SOC access during boot process. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6qdl-mba6: add boot phase propertiesMax Merchel
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. MBa6 need I2C, GPIO, SD-Card, UART and watchdog access during boot process. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6qdl-tqma6: add boot phase propertiesMax Merchel
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. TQMa6 need eMMC, I2C, GPIO, regulator and QSPI access during boot process. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6qdl: add boot phase propertiesMax Merchel
dtschema/schemas/bootph.yaml describe various node usage during boot phases with DT. All SoCs require buses (aips and spba), clock, iomuxc, ipu and SOC access during boot process. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6qdl-tqma6: add missing labelsMax Merchel
Add the missing labels for the temperature sensor and the EEPROM. In SoM variants A and B, the components are connected to different I2C buses. These labels are needed to reference them in subsequent device trees. Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: add required clocks and clock-names for ccmFrank Li
Add required clocks and clock-names for ccm to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dtb: clock-controller@20c4000 (fsl,imx6q-ccm): clock-names:0: 'osc' was expected from schema $id: http://devicetree.org/schemas/clock/imx6q-clock.yaml# Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6qdl: add label for system clocksFrank Li
Add label for system clocks and add two missing clocks anaclk[1,2]. Prepare for fixing ccm related CHECK_DTB warnings. Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx28-tx28: remove undocumented aliasesFrank Li
Remove undocumented aliases, which is not used in kernel to fix CHECK_DTBS warnings. arch/arm/boot/dts/nxp/mxs/imx28-tx28.dtb: aliases: 'lcdif_23bit_pins', 'lcdif_24bit_pins', 'reg_can_xcvr', 'spi_gpio', 'spi_mxs' do not match any of the regexes: '^[a-z][a-z0-9\\-]*$', '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/aliases.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx28-tx28: rename compatible to "edt,edt-ft5206"Frank Li
The compatible string "edt,edt-ft5x06" is neither documented nor used. According to drivers/input/touchscreen/edt-ft5x06.c, ft5206, ft5306 and ft5406 are compatible. Use "edt,edt-ft5206" instead, as the datasheet does not specify the exact touchscreen model. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx28-sps1: remove undocumented fallback compatible "mr25h256"Frank Li
Remove the undocumented fallback compatible string "mr25h256", as the SPI core strips the vendor prefix. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/mxs/imx28-sps1.dtb: /apb@80000000/apbh-bus@80000000/spi@80014000/flash@0: failed to match any schema with compatible: ['everspin,mr25h256', 'mr25h256'] Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx28: rename gpios-reset to reset-gpios of hx8357Frank Li
Rename gpios-reset to reset-gpios of hx8357 node to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dtb: hx8357@0 (himax,hx8357b): Unevaluated properties are not allowed ('gpios-reset' was unexpected) Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx23/28: add "led-" prefix to LED subnodesFrank Li
Add the "led-" prefix to LED subnodes to fix the below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dtb: leds (gpio-leds): 'user' does not match any of the regexes: '(^led-[0-9a-f]$|led)', '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/leds/leds-gpio.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx23: fix interrupt names for dma-controller@80024000Frank Li
There are duplicate "empty" entries in the interrupt-names property of the DMA controller. Rename them to "empty<n>" to fix below CHECK_DTBS warnings. arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dtb: dma-controller@80024000 (fsl,imx23-dma-apbx): interrupt-names:15: 'empty5' was expected Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx27: remove fsl,imx-osc26m from fixed-clock nodeFrank Li
Remove fsl,imx-osc26m from fixed-clock node to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx27-apf27.dtb: osc26m (fsl,imx-osc26m): compatible: ['fsl,imx-osc26m', 'fixed-clock'] is too long from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx27-eukrea-cpuimx27: rename uart8250 to serialFrank Li
Rename node name uart8250 to serial to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dtb: uart8250@3,200000 (ns8250): $nodename:0: 'uart8250@3,200000' does not match '^serial(@.*)?$' Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx27-eukrea: replace interrupts with interrupts-extendedFrank Li
The property interrupts use default interrupt controllers. But pass down gpio<n> as phandle. Correct it by use interrupts-extended. Fixes: d8cae888aa2bc ("ARM: dts: Add support for the cpuimx27 board from Eukrea and its baseboard") Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: remove redundant intermediate node in pinmux hierarchyFrank Li
Remove the redundant intermediate node between the pinmux and group nodes, and add the missing "grp" suffix to the group node names. Fix below CHECK_DTBS warnings: arm/boot/dts/nxp/imx/imx27-apf27dev.dtb: iomuxc@10015000 (fsl,imx27-iomuxc): Unevaluated properties are not allowed ('imx27-apf27', 'imx27-apf27dev' were unexpected) from schema $id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx: rename iomuxc to pinmuxFrank Li
Rename node name iomuxc to pinmux. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx1-apf9328.dtb: iomuxc@21c000 (fsl,imx1-iomuxc): $nodename:0: 'iomuxc@21c000' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' from schema $id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-04-05ARM: dts: imx6ull-dhcor: Handle both 1DX and 1YN WiFi on i.MX6ULL DHCORMarek Vasut
The muRata 1DX WiFi/BT chip is mounted on the DHCOM i.MX6ULL. This chip has been discontinued and replaced by the muRata 1YN chip. The new chip is a drop-in replacement of the old chip. To support both chips for the i.MX6ULL DHCOR, drop the more specific compatible string and let the driver auto-detect the chip type. Currently, there are no known quirks that would apply only to one or the other chip. Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-11 15:19:51 +0000