summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2026-03-26arm64: dts: qcom: kaanapali: Fix GIC_ITS range lengthKonrad Dybcio
Currently, the GITS_SGIR register is cut off. Fix it up. Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-topic-its_range_fixup-v1-1-49be8076adb1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8750-mtp: Enable DisplayPort over USBKrzysztof Kozlowski
Hook up DisplayPort parts over Type-C USB on MTP8750. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-4-fb53371e251c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8750-mtp: Enable USB headset and Type-C accessory modeKrzysztof Kozlowski
MTP8750 does not have audio jack connected and relies on USB mux (WCD9395). Add necessary nodes for proper audio headset support along with USB Type-C accessory mode and orientation. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-3-fb53371e251c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8750-mtp: Enable displayKrzysztof Kozlowski
Enable display on MTP8750 board with Novatek NT37801 panel. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-2-fb53371e251c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8750: Add display (MDSS) with Display CCKrzysztof Kozlowski
Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-sm8750-display-dts-v5-1-fb53371e251c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8750: correct Iris corners for the MXC railDmitry Baryshkov
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: c0d11ff90475 ("arm64: dts: qcom: sm8750: Add Iris VPU v3.5") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-6-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8650: correct Iris corners for the MXC railDmitry Baryshkov
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: 56cf5ad39a55 ("arm64: dts: qcom: sm8650: add iris DT node") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-5-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8550: correct Iris corners for the MXC railDmitry Baryshkov
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: 41661853ae8e ("arm64: dts: qcom: sm8550: add iris DT node") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-4-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: monaco: correct Iris corners for the MXC railDmitry Baryshkov
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: bf6ec39c3f36 ("arm64: dts: qcom: qcs8300: add video node") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-3-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: lemans: correct Iris corners for the MXC railDmitry Baryshkov
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: 7bc95052c64f ("arm64: dts: qcom: sa8775p: add support for video node") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-2-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: hamoa: correct Iris corners for the MXC railDmitry Baryshkov
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always match the PLL corners on the MXC rail. Correct the performance corners for the MXC rail following the PLL documentation. Fixes: 9065340ac04d ("arm64: dts: qcom: x1e80100: Add IRIS video codec") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-1-32a393c25dda@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: milos: add ADSP GPRLuca Weiss
Add the ADSP Generic Packet Router (GPR) device node as part of audio subsystem in Qualcomm Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260306-milos-fastrpc-gpr-v1-2-893eb98869ce@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: milos: Add fastrpc nodesLuca Weiss
Add fastrpc nodes for both ADSP and CDSP. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260306-milos-fastrpc-gpr-v1-1-893eb98869ce@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: eliza: Enable Eliza MTP board supportAbel Vesa
The MTP is a one of the boards that comes with the Eliza SoC. So add dedicated board dts for it. The initial support enables: - UART debug console - Ob-board UFS storage - Qualcomm RPMh regulators (PMIC) and VPH_PWR - board specific clocks & reserved GPIO ranges Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260318-eliza-base-dt-v3-3-8a50bd2201ed@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: Introduce Eliza Soc base dtsiAbel Vesa
Introduce the initial support for the Qualcomm Eliza SoC. It comes in different flavors. There is SM7750 for mobiles and then QC7790S/M for IoT. Describe the common parts under a common dtsi. The initial submission enables support for: - CPU nodes with cpufreq and cpuidle support - Global Clock Controller (GCC) - Resource State Coordinator (RSC) with clock controller & genpd provider - Interrupt controller - Power Domain Controller (PDC) - Vendor specific SMMU - SPMI bus arbiter - Top Control and Status Register (TCSR) - Top Level Mode Multiplexer (TLMM) - Debug UART - Reserved memory nodes - Interconnect providers - System timer - UFS Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260318-eliza-base-dt-v3-2-8a50bd2201ed@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: Add Mahua SoC and CRDGopikrishna Garmidi
Introduce support for the Mahua SoC and the CRD based on it. Some of the notable differences are the absent CPU cluster, interconnect, TLMM, thermal zones and adjusted PCIe west clocks. Everything else should work as-is. Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: Commonize Glymur CRD DTSIGopikrishna Garmidi
Commonize the existing Glymur CRD DTSI to allow reuse with Mahua CRDs. Leave the PCIe3b nodes disabled by default, since the UEFI has the instance disabled to avoid boot delays due to link failures. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260318124100.212992-3-gopikrishna.garmidi@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: hamoa-iot-evk: Update TSENS thermal zone configurationGaurav Kohli
Hamoa IOT boards support a different thermal junction temperature specification compared to the base Hamoa platform due to package level differences. Update the passive trip thresholds to 105°C to align with the higher temperature specification. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260302-higher_tj-v1-1-4c0d288f8e7f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: qcs8300-ride: Enable Bluetooth supportWei Deng
Enable BT on qcs8300-ride by adding a BT device tree node. Since the platform uses the QCA6698 Bluetooth chip. While the QCA6698 shares the same IP core as the WCN6855, it has different RF components and RAM sizes, requiring new firmware files. Use the firmware-name property to specify the NVM and rampatch firmware to load. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260302024658.2836798-1-wei.deng@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: qcs8300-ride: enable WLAN on qcs8300-rideWei Zhang
Enable WLAN on qcs8300-ride by adding a node for the PMU module of the WCN6855 and assigning its LDO power outputs to the existing WiFi module. On the qcs8300-ride platform, the corresponding firmware and BDF are QCA6698AQ instead of WCN6855, which have been added in the 20250211 release. Signed-off-by: Wei Zhang <wei.zhang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260225071459.1600394-1-wei.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: hamoa-iot-evk: Add SDC2 node for hamoa iot evk boardSarthak Garg
Enable SD Card host controller for hamoa iot evk board. Signed-off-by: Sarthak Garg <sarthak.garg@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260227040201.3700324-1-sarthak.garg@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: add missing denali-oled.dtb to MakefileTobias Heider
The DeviceTree for the OLED variant of the Microsoft Surface Pro 11th Edition was originally added in commit '0d72ccaa1e84 ("arm64: dts: qcom: Add support for X1-based Surface Pro 11")'. The original patch on the mailing list also added the new device tree to the Makefile but that part seems to have been dropped (by accident) when it got merged. Signed-off-by: Tobias Heider <tobias.heider@canonical.com> Fixes: 0d72ccaa1e84 ("arm64: dts: qcom: Add support for X1-based Surface Pro 11") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260226140429.232544-3-tobias.heider@canonical.com [bjorn: Rewrote commit message reference to offending commit] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: msm8939-asus-z00t: add ambient light and proximity sensorErikas Bitovtas
This device uses Capella CM36686 as its ambient light and proximity sensor. It is fully compatible with Vishay VCNL4040. Downstream device tree reports Capella CM36283, but upon probe, a device ID for CM36686 is actually found. This commit adds support for Capella CM36686 ambient light and proximity sensor. Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260225-z00t-capella-sensor-v1-1-99f767bc326a@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: pm6125: Enable RTC by defaultBiswapriyo Nath
sm6125 soc uses this for real time clock. Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-5-fb3ee94922d0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm6125-xiaomi-ginkgo: Enable debug UARTBiswapriyo Nath
Enable the debug uart node in xiaomi ginkgo exposed as test points. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-4-fb3ee94922d0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm6125: Add debug UART nodeBiswapriyo Nath
qup0 on sm6125 has 6 SEs and SE4 is used as debug uart. The uart node and the associated pinctrl are added here. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-3-fb3ee94922d0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm6125: Add PRNG nodeBiswapriyo Nath
Add a node for the PRNG to enable hardware accelerated pseudo random number generation. Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-2-fb3ee94922d0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm6125-xiaomi-ginkgo: Fix volume up buttonBiswapriyo Nath
gpio6 in pm6125 is used for EMMC and UFS thermal monitoring. It is changed to the correct gpio for volume up button. Fixes: 9b1a6c925c88 ("arm64: dts: qcom: sm6125: Initial support for xiaomi-ginkgo") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-1-fb3ee94922d0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: monaco-evk-camera: Add DT overlayNihal Kumar Gupta
Monaco EVK board does not include a camera sensor in its default hardware configuration. Introducing a device tree overlay to support optional integration of the IMX577 sensor via CSIPHY1. Camera reset is handled through an I2C expander, and power is enabled via TLMM GPIO74. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1 Co-developed-by: Ravi Shankar <quic_rshankar@quicinc.com> Signed-off-by: Ravi Shankar <quic_rshankar@quicinc.com> Co-developed-by: Vishal Verma <quic_vishverm@quicinc.com> Signed-off-by: Vishal Verma <quic_vishverm@quicinc.com> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213132058.521474-6-quic_nihalkum@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: monaco-evk: Add camera AVDD regulatorsNihal Kumar Gupta
Define three fixed regulators for camera AVDD rails, each gpio-controlled with corresponding pinctrl definitions. Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20260213132058.521474-5-quic_nihalkum@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: monaco: Add camera MCLK pinctrlNihal Kumar Gupta
Define pinctrl definitions to enable camera master clocks on Monaco. Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20260213132058.521474-4-quic_nihalkum@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: monaco: Add CCI definitionsNihal Kumar Gupta
Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). Compared to Lemans, the key difference is in SDA/SCL GPIO assignments and number of CCIs. Co-developed-by: Ravi Shankar <quic_rshankar@quicinc.com> Signed-off-by: Ravi Shankar <quic_rshankar@quicinc.com> Co-developed-by: Vishal Verma <quic_vishverm@quicinc.com> Signed-off-by: Vishal Verma <quic_vishverm@quicinc.com> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Nihal Kumar Gupta <quic_nihalkum@quicinc.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213132058.521474-3-quic_nihalkum@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: milos-fairphone-fp6: Add Hall Effect sensorLuca Weiss
Add a node for the Hall Effect sensor, used to detect whether the Flip Cover is closed or not. The sensor is powered through vreg_l10b, so let's put a regulator-always-on on that to make sure the sensor gets power. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213-fp6-hall-sensor-v2-1-ecd113d4919c@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge nodeAyushi Makhija
Add anx7625 DSI to DP bridge device node. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260217090955.2446470-3-quic_amakhija@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: qcs8300: add Display Serial Interface device nodesAyushi Makhija
Add device tree nodes for the DSI0 controller with their corresponding PHY found on Qualcomm QCS8300 SoC. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260217090955.2446470-2-quic_amakhija@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: milos: Sort pinctrl subnodes by pinsLuca Weiss
As documented in the "Devicetree Sources (DTS) Coding Style" document, pinctrl subnodes should be sorted by the pins property. Do this once for milos.dtsi so that future additions can be added at the right places. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213-milos-pinctrl-sort-v1-1-799bae597074@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: qrb2210-arduino-imola: describe DSI / DP bridgeDmitry Baryshkov
Aruino Uno-Q uses Analogix ANX7625 DSI-to-DP bridge to convert DSI signals to the connected USB-C DisplayPort dongles. Decribe the chip, USB-C connector and routing of USB and display signals. Co-developed-by: Martino Facchin <m.facchin@arduino.cc> Signed-off-by: Martino Facchin <m.facchin@arduino.cc> Tested-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213-uno-q-anx7625-v2-1-c23359616528@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: arduino-imola: fix faulty spidev nodeRiccardo Mereu
CS pin added on pinctrl0 property is causing spidev to return -ENODEV since that GPIO is already part of spi5 pinmuxing. Fixes: 3f745bc0f11f ("arm64: dts: qcom: qrb2210: add dts for Arduino unoq") Signed-off-by: Riccardo Mereu <r.mereu@arduino.cc> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213101002.105238-1-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm8550: Add UART15Xilin Wu
Add uart15 node for UART bus present on sm8550 SoC. Signed-off-by: Molly Sophia <mollysophia379@gmail.com> Signed-off-by: Xilin Wu <wuxilin123@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260212-sm8550-uart15-v3-1-b90405f94bec@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Add Focaltech FT3518 touchscreenYedaya Katsman
Add device tree node for the Focaltech FT3518 touchscreen on Xiaomi Mi A3 (laurel-sprout). Enable qupv3_id_0 and i2c2 bus that the touchscreen is on. Downstream references: Link: https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/laurel-r-oss/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi Link: https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/laurel-r-oss/arch/arm64/boot/dts/qcom/laurel_sprout-qrd.dtsi Co-developed-by: Kamil Gołda <kamil.golda@protonmail.com> Signed-off-by: Kamil Gołda <kamil.golda@protonmail.com> Signed-off-by: Yedaya Katsman <yedaya.ka@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260208-touchscreen-patches-v5-1-5821dff9c9a2@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: x1-asus-zenbook-a14: add HDMI portAleksandrs Vinarskis
Add HDMI port that utilizes qmpphy via Parade PS185HDM DP-HDMI bridge. Based on commit 34d76723c410 ("arm64: dts: qcom: x1e80100-vivobook-s15: add HDMI port") Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260211-zenbook-a14-improvements-v1-1-d970af6e25a3@vinarskis.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: hamoa-iot-som: Add firmware-name to QUPv3 nodesXueyao An
Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260212082558.2811953-1-xueyao.an@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26arm64: dts: qcom: kodiak: Add I2S1 pinctrl definitionsLuca Weiss
Add the pinctrl definitions to configure gpio6-gpio9 of the lpass_tlmm for I2S output. Co-developed-by: Bharadwaj Raju <bharadwaj.raju@machinesoul.in> Signed-off-by: Bharadwaj Raju <bharadwaj.raju@machinesoul.in> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260211-kodiak-i2s1-v1-1-b3a7fad8014e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26riscv: dts: spacemit: Add ethernet device for K3Inochi Amaoto
Add all ethernet device nodes for K3 SoC. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-03-26LoongArch: KVM: Fix base address calculation in kvm_eiointc_regs_access()Bibo Mao
In function kvm_eiointc_regs_access(), the register base address is caculated from array base address plus offset, the offset is absolute value from the base address. The data type of array base address is u64, it should be converted into the "void *" type and then plus the offset. Cc: <stable@vger.kernel.org> Fixes: d3e43a1f34ac ("LoongArch: KVM: Use 64-bit register definition for EIOINTC"). Reported-by: Aurelien Jarno <aurel32@debian.org> Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1131431 Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-03-26LoongArch: KVM: Handle the case that EIOINTC's coremap is emptyHuacai Chen
EIOINTC's coremap in eiointc_update_sw_coremap() can be empty, currently we get a cpuid with -1 in this case, but we actually need 0 because it's similar as the case that cpuid >= 4. This fix an out-of-bounds access to kvm_arch::phyid_map::phys_map[]. Cc: <stable@vger.kernel.org> Fixes: 3956a52bc05bd81 ("LoongArch: KVM: Add EIOINTC read and write functions") Reported-by: Aurelien Jarno <aurel32@debian.org> Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1131431 Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-03-26LoongArch: KVM: Make kvm_get_vcpu_by_cpuid() more robustHuacai Chen
kvm_get_vcpu_by_cpuid() takes a cpuid parameter whose type is int, so cpuid can be negative. Let kvm_get_vcpu_by_cpuid() return NULL for this case so as to make it more robust. This fix an out-of-bounds access to kvm_arch::phyid_map::phys_map[]. Cc: <stable@vger.kernel.org> Fixes: 73516e9da512adc ("LoongArch: KVM: Add vcpu mapping from physical cpuid") Reported-by: Aurelien Jarno <aurel32@debian.org> Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1131431 Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-03-26LoongArch: vDSO: Emit GNU_EH_FRAME correctlyXi Ruoyao
With -fno-asynchronous-unwind-tables and --no-eh-frame-hdr (the default of the linker), the GNU_EH_FRAME segment (specified by vdso.lds.S) is empty. This is not valid, as the current DWARF specification mandates the first byte of the EH frame to be the version number 1. It causes some unwinders to complain, for example the ClickHouse query profiler spams the log with messages: clickhouse-server[365854]: libunwind: unsupported .eh_frame_hdr version: 127 at 7ffffffb0000 Here "127" is just the byte located at the p_vaddr (0, i.e. the beginning of the vDSO) of the empty GNU_EH_FRAME segment. Cross- checking with /proc/365854/maps has also proven 7ffffffb0000 is the start of vDSO in the process VM image. In LoongArch the -fno-asynchronous-unwind-tables option seems just a MIPS legacy, and MIPS only uses this option to satisfy the MIPS-specific "genvdso" program, per the commit cfd75c2db17e ("MIPS: VDSO: Explicitly use -fno-asynchronous-unwind-tables"). IIRC it indicates some inherent limitation of the MIPS ELF ABI and has nothing to do with LoongArch. So we can simply flip it over to -fasynchronous-unwind-tables and pass --eh-frame-hdr for linking the vDSO, allowing the profilers to unwind the stack for statistics even if the sample point is taken when the PC is in the vDSO. However simply adjusting the options above would exploit an issue: when the libgcc unwinder saw the invalid GNU_EH_FRAME segment, it silently falled back to a machine-specific routine to match the code pattern of rt_sigreturn() and extract the registers saved in the sigframe if the code pattern is matched. As unwinding from signal handlers is vital for libgcc to support pthread cancellation etc., the fall-back routine had been silently keeping the LoongArch Linux systems functioning since Linux 5.19. But when we start to emit GNU_EH_FRAME with the correct format, fall-back routine will no longer be used and libgcc will fail to unwind the sigframe, and unwinding from signal handlers will no longer work, causing dozens of glibc test failures. To make it possible to unwind from signal handlers again, it's necessary to code the unwind info in __vdso_rt_sigreturn via .cfi_* directives. The offsets in the .cfi_* directives depend on the layout of struct sigframe, notably the offset of sigcontext in the sigframe. To use the offset in the assembly file, factor out struct sigframe into a header to allow asm-offsets.c to output the offset for assembly. To work around a long-term issue in the libgcc unwinder (the pc is unconditionally substracted by 1: doing so is technically incorrect for a signal frame), a nop instruction is included with the two real instructions in __vdso_rt_sigreturn in the same FDE PC range. The same hack has been used on x86 for a long time. Cc: stable@vger.kernel.org Fixes: c6b99bed6b8f ("LoongArch: Add VDSO and VSYSCALL support") Signed-off-by: Xi Ruoyao <xry111@xry111.site> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-03-26LoongArch: Workaround LS2K/LS7A GPU DMA hang bugHuacai Chen
1. Hardware limitation: GPU, DC and VPU are typically PCI device 06.0, 06.1 and 06.2. They share some hardware resources, so when configure the PCI 06.0 device BAR1, DMA memory access cannot be performed through this BAR, otherwise it will cause hardware abnormalities. 2. In typical scenarios of reboot or S3/S4, DC access to memory through BAR is not prohibited, resulting in GPU DMA hangs. 3. Workaround method: When configuring the 06.0 device BAR1, turn off the memory access of DC, GPU and VPU (via DC's CRTC registers). Cc: stable@vger.kernel.org Signed-off-by: Qianhai Wu <wuqianhai@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-03-26LoongArch: Fix missing NULL checks for kstrdup()Li Jun
1. Replace "of_find_node_by_path("/")" with "of_root" to avoid multiple calls to "of_node_put()". 2. Fix a potential kernel oops during early boot when memory allocation fails while parsing CPU model from device tree. Cc: stable@vger.kernel.org Signed-off-by: Li Jun <lijun01@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-13 21:55:52 +0000