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2026-03-11sparc64: vdso: Use 32-bit CHECKFLAGS for compat vDSOThomas Weißschuh
When building the compat vDSO the CHECKFLAGS from the 64-bit kernel are used. These are combined with the 32-bit CFLAGS. This confuses sparse, producing false-positive warnings or potentially missing real issues. Manually override the CHECKFLAGS for the compat vDSO with the correct 32-bit configuration. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260302-vdso-compat-checkflags-v2-2-78e55baa58ba@linutronix.de Closes: https://lore.kernel.org/lkml/202511030021.9v1mIgts-lkp@intel.com/
2026-03-11x86/vdso: Use 32-bit CHECKFLAGS for compat vDSOThomas Weißschuh
When building the compat vDSO the CHECKFLAGS from the 64-bit kernel are used. These are combined with the 32-bit CFLAGS. This confuses sparse, producing false-positive warnings or potentially missing real issues. Manually override the CHECKFLAGS for the compat vDSO with the correct 32-bit configuration. Reported-by: Sun Jian <sun.jian.kdev@gmail.com> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260302-vdso-compat-checkflags-v2-1-78e55baa58ba@linutronix.de Closes: https://lore.kernel.org/lkml/20260114084529.1676356-1-sun.jian.kdev@gmail.com/ Closes: https://lore.kernel.org/lkml/20260117215542.342638347@kernel.org/ Closes: https://lore.kernel.org/r/202602111941.PIhubgrb-lkp@intel.com/
2026-03-11KVM: arm64: Add selftest event support to nVHE/pKVM hypVincent Donnefort
Add a selftest event that can be triggered from a `write_event` tracefs file. This intends to be used by trace remote selftests. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-30-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add hyp_enter/hyp_exit events to nVHE/pKVM hypVincent Donnefort
The hyp_enter and hyp_exit events are logged by the hypervisor any time it is entered and exited. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-29-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add event support to the nVHE/pKVM hyp and trace remoteVincent Donnefort
Allow the creation of hypervisor and trace remote events with a single macro HYP_EVENT(). That macro expands in the kernel side to add all the required declarations (based on REMOTE_EVENT()) as well as in the hypervisor side to create the trace_<event>() function. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-28-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add trace reset to the nVHE/pKVM hypVincent Donnefort
Make the hypervisor reset either the whole tracing buffer or a specific ring-buffer, on remotes/hypervisor/trace or per_cpu/<cpu>/trace write access. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-27-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Sync boot clock with the nVHE/pKVM hypVincent Donnefort
Configure the hypervisor tracing clock with the kernel boot clock. For tracing purposes, the boot clock is interesting: it doesn't stop on suspend. However, it is corrected on a regular basis, which implies the need to re-evaluate it every once in a while. Cc: John Stultz <jstultz@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Christopher S. Hall <christopher.s.hall@intel.com> Cc: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-26-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add trace remote for the nVHE/pKVM hypVincent Donnefort
In both protected and nVHE mode, the hypervisor is capable of writing events into tracefs compatible ring-buffers. Create a trace remote so the kernel can read those buffers. This currently doesn't provide any event support which will come later. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-25-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add tracing capability for the nVHE/pKVM hypVincent Donnefort
There is currently no way to inspect or log what's happening at EL2 when the nVHE or pKVM hypervisor is used. With the growing set of features for pKVM, the need for tooling is more pressing. And tracefs, by its reliability, versatility and support for user-space is fit for purpose. Add support to write into a tracefs compatible ring-buffer. There's no way the hypervisor could log events directly into the host tracefs ring-buffers. So instead let's use our own, where the hypervisor is the writer and the host the reader. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-24-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Support unaligned fixmap in the pKVM hypVincent Donnefort
Return the fixmap VA with the page offset, instead of the page base address. This allows to use hyp_fixmap_map() seamlessly regardless of the address alignment. While at it, do the same for hyp_fixblock_map(). Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-23-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Initialise hyp_nr_cpus for nVHE hypVincent Donnefort
Knowing the number of CPUs is necessary for determining the boundaries of per-cpu variables, which will be used for upcoming hypervisor tracing. hyp_nr_cpus which stores this value, is only initialised for the pKVM hypervisor. Make it accessible for the nVHE hypervisor as well. With the kernel now responsible for initialising hyp_nr_cpus, the nr_cpus parameter is no longer needed in __pkvm_init. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-22-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add clock support to nVHE/pKVM hypVincent Donnefort
In preparation for supporting tracing from the nVHE hyp, add support to generate timestamps with a clock fed by the CNTCVT counter. The clock can be kept in sync with the kernel's by updating the slope values. This will be done later. As current we do only create a trace clock, make the whole support dependent on the upcoming CONFIG_NVHE_EL2_TRACING. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-21-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11KVM: arm64: Add PKVM_DISABLE_STAGE2_ON_PANICVincent Donnefort
On NVHE_EL2_DEBUG, when using pKVM, the host stage-2 is relaxed to grant the kernel access to the stacktrace, hypervisor bug table and text to symbolize addresses. This is unsafe for production. In preparation for adding more debug options to NVHE_EL2_DEBUG, decouple the stage-2 relaxation into a separate option. While at it, rename PROTECTED_NVHE_STACKTRACE into PKVM_STACKTRACE, following the same naming scheme as PKVM_DISABLE_STAGE2_ON_PANIC. Reviewed-by: Kalesh Singh <kaleshsingh@google.com> Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260309162516.2623589-20-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-03-11arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NANDChen-Yu Tsai
The Avaota A1 board has a SPI NAND chip connected to spi0 on the PJ pins with support for QSPI. Enable spi0 and add a device node for the SPI NAND chip. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20260302153559.3199783-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-03-11arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pinsChen-Yu Tsai
The Avaota A1 board uses spi0 on the PJ pins to connect a SPI NAND chip. Add the full set of pins. Even though this board doesn't use CS1, other boards may do so in the future. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20260302153559.3199783-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-03-10x86/64/defconfig: Add CONFIG_IRQ_REMAPShashank Balaji
x2apic is enabled in the defconfig, and interrupt remapping is an architectural dependency of x2apic as per the Intel SDM: Routing of device interrupts to local APIC units operating in x2APIC mode requires use of the interrupt-remapping architecture specified in the Intel® Virtualization Technology for Directed I/O (Revision 1.3 and/or later versions). Enable CONFIG_IRQ_REMAP in defconfig so that a defconfig kernel on bare metal actually uses x2apic. Co-developed-by: Rahul Bukte <rahul.bukte@sony.com> Signed-off-by: Rahul Bukte <rahul.bukte@sony.com> Signed-off-by: Shashank Balaji <shashank.mahadasyam@sony.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Acked-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260306-x2apic-fix-v2-2-bee99c12efa3@sony.com
2026-03-10arm64: remove ARCH_INLINE_*Jisheng Zhang
Since commit 7dadeaa6e851 ("sched: Further restrict the preemption modes"), arm64 only has two preemption models: full and lazy. Both implies PREEMPTION, so !PREEMPTION is always false for arm64, it's time to remove ARCH_INLINE_*. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2026-03-10arm64: dts: exynos8895: Move I2C address/size-cells to DTSIKrzysztof Kozlowski
Convention followed in all other DTSI files is to define I2C controller address/size-cells in the DTSI thus reducing code needed in each DTS. It's also logical, since I2C is a bus and needs definition of addressing children, even if the bus is enabled without the nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-2-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-10arm64: dts: exynos7870: Move I2C address/size-cells to DTSIKrzysztof Kozlowski
Convention followed in all other DTSI files is to define I2C controller address/size-cells in the DTSI thus reducing code needed in each DTS. It's also logical, since I2C is a bus and needs definition of addressing children, even if the bus is enabled without the nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-1-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-10ARM: dts: exyons4412: Drop duplicated I2C address/size-cellsKrzysztof Kozlowski
The DTSI already has address/size-cells for each I2C controller, thus the board does not have to define them again. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-5-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-10ARM: dts: exynos4210-smdkv310: Drop duplicated I2C address/size-cellsKrzysztof Kozlowski
The DTSI already has address/size-cells for each I2C controller, thus the board does not have to define them again. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-4-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-10ARM: dts: exynos3250: Drop duplicated I2C address/size-cellsKrzysztof Kozlowski
The DTSI already has address/size-cells for each I2C controller, thus the board does not have to define them again. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-3-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-10arm64: dts: allwinner: sun55i-t527: avaota-a1: Enable LEDsChen-Yu Tsai
The Avaota A1 board features 4 RGB LEDs in a string connected to the SoC's LED controller. Enable the LED controller and add device nodes for them. The timings were copied from the downstream vendor DTS. The design does not specify what these LEDs are for, nor are there any markings on the board for them, so just use them as indicators. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20260302152724.3197587-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-03-10arm64: dts: allwinner: sun55i-a523: Add LED controllerChen-Yu Tsai
The A523 SoC family features an LED controller that is identical to the one found on previous SoCs. Add a device node for it, and one of the possible pinmux settings. This setting is used on the Avaota A1. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20260302152724.3197587-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-03-10x86/apic: Disable x2apic on resume if the kernel expects soShashank Balaji
When resuming from s2ram, firmware may re-enable x2apic mode, which may have been disabled by the kernel during boot either because it doesn't support IRQ remapping or for other reasons. This causes the kernel to continue using the xapic interface, while the hardware is in x2apic mode, which causes hangs. This happens on defconfig + bare metal + s2ram. Fix this in lapic_resume() by disabling x2apic if the kernel expects it to be disabled, i.e. when x2apic_mode = 0. The ACPI v6.6 spec, Section 16.3 [1] says firmware restores either the pre-sleep configuration or initial boot configuration for each CPU, including MSR state: When executing from the power-on reset vector as a result of waking from an S2 or S3 sleep state, the platform firmware performs only the hardware initialization required to restore the system to either the state the platform was in prior to the initial operating system boot, or to the pre-sleep configuration state. In multiprocessor systems, non-boot processors should be placed in the same state as prior to the initial operating system boot. (further ahead) If this is an S2 or S3 wake, then the platform runtime firmware restores minimum context of the system before jumping to the waking vector. This includes: CPU configuration. Platform runtime firmware restores the pre-sleep configuration or initial boot configuration of each CPU (MSR, MTRR, firmware update, SMBase, and so on). Interrupts must be disabled (for IA-32 processors, disabled by CLI instruction). (and other things) So at least as per the spec, re-enablement of x2apic by the firmware is allowed if "x2apic on" is a part of the initial boot configuration. [1] https://uefi.org/specs/ACPI/6.6/16_Waking_and_Sleeping.html#initialization [ bp: Massage. ] Fixes: 6e1cb38a2aef ("x64, x2apic/intr-remap: add x2apic support, including enabling interrupt-remapping") Co-developed-by: Rahul Bukte <rahul.bukte@sony.com> Signed-off-by: Rahul Bukte <rahul.bukte@sony.com> Signed-off-by: Shashank Balaji <shashank.mahadasyam@sony.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260306-x2apic-fix-v2-1-bee99c12efa3@sony.com
2026-03-10KVM: arm64: pkvm: Don't reprobe for ICH_VTR_EL2.TDS on CPU hotplugMarc Zyngier
Hotplugging a CPU off and back on fails with pKVM, as we try to probe for ICH_VTR_EL2.TDS. In a non-VHE setup, this is achieved by using an EL2 stub helper. However, the stubs are out of reach once pKVM has deprivileged the kernel. The CPU never boots. Since pKVM doesn't allow late onlining of CPUs, we can detect that protected mode is enforced early on, and return the current state of the capability. Fixes: 2a28810cbb8b2 ("KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping") Reported-by: Vincent Donnefort <vdonnefort@google.com> Tested-by: Vincent Donnefort <vdonnefort@google.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260310085433.3936742-1-maz@kernel.org Cc: stable@vger.kernel.org
2026-03-10arm64: dts: ti: k3-am62l-main: Add RNG nodeShiva Tripathi
Add EIP76 Random Number Generator (RNG) node for AM62L SoC. Unlike other k3 platforms, AM62L RNG is integrated outside crypto subsystem at address 0x3b100000, requiring an additional entry in cbass_main memory map. Mark the RNG node with status "reserved" as it is intended for use by OP-TEE for secure random number generation. If required, this hardware can also be used through Linux kernel by enabling this node. Signed-off-by: Shiva Tripathi <s-tripathi1@ti.com> Link: https://patch.msgid.link/20260309101650.1652240-1-s-tripathi1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: remove the Kontron SMARC-sAM67Michael Walle
I was just informed that this product is discontinued (without being ever released to the market). Pull the plug and let's not waste any more maintainers time. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://patch.msgid.link/20260302122540.1377444-2-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-j721s2-common-proc-board: Add QSPI flash partition detailsAnurag Dutta
J721S2 EVM has MT25QU512AB 64 MiB Quad SPI NOR flash connected to OSPI1. Add the partition information as per bootloader. Signed-off-by: Anurag Dutta <a-dutta@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://patch.msgid.link/20260226091730.2735587-1-a-dutta@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-j721e-common-proc-board: add ti,min-output-impedanceSiddharth Vadapalli
The default impedance for the MAC I/O lines from the DP83867 Ethernet PHY is 50 Ohm. Based on the board PCB traces, this impedance is relatively higher than expected, resulting in CRC errors for packets being transmitted and received. Hence, add the "ti,min-output-impedance" device-tree property to set the impedance to its lowest possible value of 35 Ohm as described in the DP83867 Datasheet [0]. [0]: https://www.ti.com/lit/ds/symlink/dp83867e.pdf Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20260223105448.1110428-5-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-j7200-common-proc-board: add ti,min-output-impedanceSiddharth Vadapalli
The default impedance for the MAC I/O lines from the DP83867 Ethernet PHY is 50 Ohm. Based on the board PCB traces, this impedance is relatively higher than expected, resulting in CRC errors for packets being transmitted and received. Hence, add the "ti,min-output-impedance" device-tree property to set the impedance to its lowest possible value of 35 Ohm as described in the DP83867 Datasheet [0]. [0]: https://www.ti.com/lit/ds/symlink/dp83867e.pdf Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20260223105448.1110428-4-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-am654-base-board: add ti,min-output-impedanceSiddharth Vadapalli
The default impedance for the MAC I/O lines from the DP83867 Ethernet PHY is 50 Ohm. Based on the board PCB traces, this impedance is relatively higher than expected, resulting in CRC errors for packets being transmitted and received. Hence, add the "ti,min-output-impedance" device-tree property to set the impedance to its lowest possible value of 35 Ohm as described in the DP83867 Datasheet [0]. [0]: https://www.ti.com/lit/ds/symlink/dp83867e.pdf Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20260223105448.1110428-3-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-am642-{evm,sk}: add ti,min-output-impedanceSiddharth Vadapalli
The default impedance for the MAC I/O lines from the DP83867 Ethernet PHY is 50 Ohm. Based on the board PCB traces, this impedance is relatively higher than expected, resulting in CRC errors for packets being transmitted and received. Hence, add the "ti,min-output-impedance" device-tree property to set the impedance to its lowest possible value of 35 Ohm as described in the DP83867 Datasheet [0]. [0]: https://www.ti.com/lit/ds/symlink/dp83867e.pdf Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20260223105448.1110428-2-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: boot: dts: ti: k3-am62l3-evm: enable wkup_uart0_target nodeKendall Willis
Change the status of the wkup_uart0_target node to enabled. The node sets the UART SYSS register to allow wakeup from WKUP UART in DeepSleep low power mode. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Kendall Willis <k-willis@ti.com> Link: https://patch.msgid.link/20260219-v6-19-wkup-uart-wakeup-v4-4-eda09dce5623@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: boot: dts: ti: k3-am62l3-evm: define wkup_uart0 pinsKendall Willis
Add the pin definition for the wkup_uart0 node. Signed-off-by: Kendall Willis <k-willis@ti.com> Link: https://patch.msgid.link/20260219-v6-19-wkup-uart-wakeup-v4-3-eda09dce5623@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: boot: dts: ti: k3-am62l-wakeup: create label for wkup_uart0 target-moduleKendall Willis
Add label to the target-module node so that it can easily be referenced. The node specifically configures the SYSCONFIG related registers for WKUP UART. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Kendall Willis <k-willis@ti.com> Link: https://patch.msgid.link/20260219-v6-19-wkup-uart-wakeup-v4-2-eda09dce5623@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-am62l: include WKUP_UART0 in wakeup peripheral windowKendall Willis
WKUP_UART0 is apart of the wakeup peripherals and has a range from 0x002B300000 to 0x002B3001FF. Expand the wakeup peripheral window to include WKUP_UART0. Fixes: 5f016758b0ab ("arm64: dts: ti: k3-am62l: add initial infrastructure") Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Kendall Willis <k-willis@ti.com> Link: https://patch.msgid.link/20260219-v6-19-wkup-uart-wakeup-v4-1-eda09dce5623@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-am62d2-evm: Set wakeup-source system-statesKendall Willis
The CANUART pins of mcu_mcan0, mcu_mcan1, mcu_uart0 and wkup_uart0 are powered during Partial-IO and I/O Only + DDR and are capable of waking up the system in these states. Specify the states in which these units can do a wakeup on this board. Note that the UARTs are not capable of wakeup in Partial-IO because of of a UART mux on the board not being powered during Partial-IO. Add pincontrol definitions for mcu_mcan0 and mcu_mcan1 for wakeup from Partial-IO. Add these as wakeup pinctrl entries for both devices. Signed-off-by: Kendall Willis <k-willis@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://patch.msgid.link/20260212-am62d-can-wkup-dts-v1-1-d2de17e1f303@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10arm64: dts: ti: k3-am62-phycore-som: Add 128MiB of global CMAWadim Egorov
Reserve 128MiB of global CMA which is also marked as re-usable so that OS can also use the same if peripheral drivers are not using the same. Based on the use case described in commit c43dd2fe5316 ("arm64: dts: ti: k3-am62x-sk-common: Reserve 128MiB of global CMA"). Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://patch.msgid.link/20260213053806.219495-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10riscv: dts: spacemit: Add 'linux,pci-domain' to PCIe nodes for K1Chukun Pan
The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the 'linux,pci-domain' property to assign a PCI domain number to each of the controllers instead of assigning it randomly. This creates a stable sysfs path, allowing userspace scripts to reliably target specific PCIe devices (such as PCIe NICs). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-03-10arm64: dts: rockchip: Enable GPU on rk3566-pinenoteSamuel Holland
The GPU is most useful when used together with the EBC on the PineNote, which is not yet described. But there's no reason not to define the GPU already as the hardware is present and could be used without the EBC. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Diederik de Haas <diederik@cknow-tech.com> Link: https://patch.msgid.link/20260305120620.173600-1-diederik@cknow-tech.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-03-09arm64: dts: qcom: correct RBR opp entryDmitry Baryshkov
DisplayPort Reduced Bit Rate uses link rate of 1.62 Gbps, the main link clock should be 162 MHz. Having the incorrect frequency (160 MHz) in the OPP table will result in selecting wrong link frequency. Correct the entry in the OPP table. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260304-msm-fix-rbr-v1-1-b9eba986eaef@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: monaco-evk: Enable the secondary USB controllerSwati Agarwal
Enable the secondary USB controller connected to micro usb port in OTG mode on Monaco EVK platform. Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260303082157.523847-4-swati.agarwal@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: monaco: Add role-switch support and HS endpoint for ↵Swati Agarwal
secondary USB controller Enable usb-role-switch for the secondary HS USB controller on Monaco. Additionally, add a port node with an HS endpoint so the controller can be linked through the DT graph to the corresponding connector. Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260303082157.523847-3-swati.agarwal@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: monaco-evk: Enable GPIO expander interrupt for Monaco EVKSwati Agarwal
Enable PCA9538 expander as interrupt controller on Monaco EVK and configure the corresponding TLMM pins via pinctrl to operate as GPIO inputs with internal pull-ups. Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260303082157.523847-2-swati.agarwal@oss.qualcomm.com [bjorn: Reordered nodes under &tlmm] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: sdm845: Introduce camera master clock pinctrlDavid Heidelberg
Put clock pins configuration for camera master clock into the dtsi. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20260114-sdm845-mclk-v3-1-c9351deaf4f2@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: qcm6490-idp: add and enable BT nodeJanaki Ramaiah Thota
Add the PMU node for WCN6750 present on the qcm6490-idp board and assign its power outputs to the Bluetooth module. In WCN6750 module sw_ctrl and wifi-enable pins are handled in the wifi controller firmware. Therefore, it is not required to have those pins' entries in the PMU node. Signed-off-by: Janaki Ramaiah Thota <janaki.thota@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260203071807.764036-1-janaki.thota@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: monaco-evk: Enable SDHC1 for eMMCLoic Poulain
Monaco EVK has onboard eMMC, that can be used either as primary boot storage or as secondary storage when booting from UFS. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260116214354.256878-3-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: monaco: Complete SDHC definitionLoic Poulain
Add the missing SDHC properties required to enable HS200, HS400, and HS400 Enhanced Strobe modes, as supported by this controller. Select the proper default pinctrls. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260116214354.256878-2-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-09arm64: dts: qcom: talos: add ETR deviceJie Gan
Add the TMC ETR device to store collected trace data in DDR memory. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260128-enable-etr-on-talos-v2-1-ba77063d6b62@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-20 16:09:17 +0000