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2026-05-31arm64: dts: renesas: r9a09g077: Add xSPI nodesLad Prabhakar
Add device tree nodes for the two xSPI (Expanded SPI) controllers integrated into the RZ/T2H (R9A09G077) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260526204045.3481604-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: rzg3e-smarc-som: Sort GMAC pinmux entriesBiju Das
Sort the pinmux entries for both GMAC ctrl nodes in port order (A/B/C and D/E/F respectively) and remove the extra blank line before the second pinmux assignment. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260524092016.46346-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD GeistNguyen Tran
Add support for the Geist board based on the Renesas R-Car R8A779MD (M3Le) SoC, a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Nguyen Tran <nguyen.tran.pz@bp.renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20260522172000.15096-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a07g044: Add DMA properties to serial nodesClaudiu Beznea
Add DMA properties to the serial nodes on the RZ/G2L SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520132315.944117-1-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodesBiju Das
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodesBiju Das
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2L,G2LC} (r9a07g044) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520115144.60067-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodesBiju Das
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2UL,Five} (r9a07g043) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520115144.60067-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a08g046: Add rsci{0..3} device nodesBiju Das
Add rsci{0..3} device nodes to the RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260519100022.116318-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: ironhide: Enable to use SCMIKuninori Morimoto
Enable SCMI via MFIS-SCP and S-TCM transport area. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260519074702.3308-6-wsa+renesas@sang-engineering.com [geert: Drop scmi_clk node] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r8a78000: Add MFIS, MFIS-SCP, and transport nodesKuninori Morimoto
Describe the MFIS and MFIS SCP instances which are used for various tasks including inter-processor communication. Remove the PRR node because it is part of MFIS on R-Car X5H and should be handled using the MFIS compatible. Also, describe the S-TCM transport area used for shared memory mailboxing. Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260519074702.3308-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: ironhide: Describe all reserved memoryMarek Vasut
Fully describe all available DRAM in the DT, and describe regions which are not accessible because they are used by firmware in reserved-memory nodes. Replace the first memory bank memory@60600000 with memory@40000000 and a 518 MiB long reserved-memory no-map subnode. This memory region is used by other cores in the system. Reserve 32 kiB of memory at 0x8c100000 for parameters shared by IPL, SCP, TFA BL31 and TEE. Reserve 512 kiB of memory at 0x8c200000 for TFA BL31. The upcoming upstream TFA 2.15 BL31 uses memory from 0x8c200000..0x8c242fff; rounding up to 512 kiB is slight future-proofing. Reserve 32 MiB of memory at 0x8c400000 for OPTEE-OS, which is the entire OPTEE-OS TZ protected DRAM area. Neither TFA BL31 nor OPTEE-OS modify the DT passed to Linux in any way with any new reserved-memory {} nodes to reserve memory areas used by the TFA BL31 or OPTEE-OS to prevent the next stage from using those areas, which lets Linux use all of the available DRAM as it is described in the DT that was passed in by U-Boot, including the areas that are newly utilized by TFA BL31 or OPTEE-OS. In case of high DRAM utilization, unless the memory used by TFA BL31 or OPTEE-OS is properly reserved, Linux may use and corrupt the memory used by TFA BL31 or OPTEE-OS, which would lead to the system becoming unresponsive. Fixes: ad142a4ef710 ("arm64: dts: renesas: r8a78000: Add initial Ironhide board support") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260517163212.18016-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pinsFabrizio Castro
The HW user manual for the Renesas RZ/T2H and the RZ/N2H states that for SDR104, SDR50, and HS200 to work properly the eMMC/SDHI interface pins have to be configured as specified below: - SDn_CLK pin - drive strength: Ultra High, slew rate: Fast, - Other SDn_* pins: drive strength: High, slew rate: Fast, Schmitt trigger: disabled (not applicable to SDn_RST pins). HS DDR and DDR50 are currently not supported, and for every other bus mode the eMMC/SDHI interface pins should be configured as specified below: - SDn_CLK pin - drive strength: High, slew rate: Fast, - Other SDn_* pins: drive strength: Middle, slew rate: Fast, Schmitt trigger: disabled (not applicable to SDn_RST pins). Adjust the pin definitions accordingly. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20260514210220.7616-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r8a78000: Fix GIC-720AE View 1 Redistributor descriptionMarek Vasut
The Renesas R-Car X5H (R8A78000) SoC contains Arm CoreLink GIC-720AE Generic Interrupt Controller with Multi View capability. Firmware has access to configuration View 0, Linux kernel has access to View 1. The Arm CoreLink GIC-720AE Generic Interrupt Controller Technical Reference Manual, currently latest r2p1 [1], chapter "5. Programmers model for GIC-720AE", subchapter "5.4 Redistributor registers for control and physical LPIs summary", part "5.4.3 GICR_TYPER, Redistributor Type Register", "Table 5-50: GICR_TYPER bit descriptions" on page 200, clarifies register "GICR_TYPER" bit 4 "Last" behavior in Multi View setup as follows: Last Last Redistributor: 0 ... This Redistributor is not the last Redistributor on the chip. 1 ... This Redistributor is the last Redistributor on the chip. When GICD_CFGID.VIEW == 1, for views 1, 2, or 3 this bit always returns 1. On this SoC, GICD_CFGID.VIEW is 1 and the Linux kernel has access to View 1, therefore Linux kernel GICv3 driver will interpret register "GICR_TYPER" bit 4 "Last" = 1 in the first Redistributor in continuous Redistributor page as that first Redistributor being the one and only Redistributor and will stop processing the continuous Redistributor page further. This will prevent the other Redistributors from being recognized by the system and used for other PEs. Because the hardware indicates that the continuous Redistributor page is not continuous for View 1, 2, or 3, describe every Redistributor separately in the DT. This makes all Redistributors for all cores accessible in Linux. [1] https://documentation-service.arm.com/static/69ef3c1cd35efd294e335c43 Arm® CoreLink™ GIC-720AE Generic Interrupt Controller Revision: r2p1 / Issue 12 / 102666_0201_12_en Fixes: 63500d12cf76 ("arm64: dts: renesas: Add R8A78000 SoC support") Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260514125328.20954-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r8a78000: Add PSCI nodeMarek Vasut
Describe SMC based PSCI access in SoC DT. The system can interact with TFA BL31 PSCI provider running on the Cortex-A cores via SMC calls. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260513225037.49803-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add alias for on-SoC RTCLad Prabhakar
The RZ/V2N SoC provides an internal RTC, which is enabled in the DT. The RZ/V2N EVK board also includes an external RTC in the RAA215300 PMIC. Add an "rtc0" alias pointing to the on-SoC RTC node to ensure a stable device numbering. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260506155804.3984418-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add alias for on-SoC RTCLad Prabhakar
The RZ/V2H SoC provides an internal RTC, which is enabled in the DT. The RZ/V2H EVK board also includes an external RTC in the RAA215300 PMIC. Add an "rtc0" alias pointing to the on-SoC RTC node to ensure a stable device numbering. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260506155804.3984418-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a08g046: Add audio clock nodesBiju Das
Add audio_clk1 and audio_clk2 fixed-clock nodes to the RZ/G3L (r9a08g046) SoC DTSI. These clocks are external to the SoC and their frequencies are board-dependent, so they are defined with clock-frequency = <0> as placeholders that must be overridden in board-level DTS files. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505123708.134069-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a08g046: Add SSI supportBiju Das
Add SSI{0,1,2,3} nodes to RZ/G3L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505123708.134069-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a08g046: Add DMAC nodeBiju Das
Add the DMA controller device tree node for the RZ/G3L (r9a08g046) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505123708.134069-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a08g046: Add i2c{0..3} device nodesBiju Das
Add i2c{0..3} device nodes to RZ/G3L ("R9A08G046") SoC DTSI. As the place holders for i2c0 is removed, add the pincontrol device nodes to make it functional on the board DTS. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505070206.7932-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a08g046: Add scif{1..5} device nodesBiju Das
Add scif{1..5} device nodes to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505070206.7932-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: gray-hawk: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-12-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: white-hawk: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-11-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: falcon: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-10-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: draak: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-9-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: ebisu: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-8-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: v3hsk: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-7-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: condor-common: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-6-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: v3msk: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: eagle: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: ulcb: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: salvator-common: Specify ethernet PHY reset timingsMarek Vasut
The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260505034325.167797-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: ulcb: Rename clk-multiplier to clock-controllerMarek Vasut
Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504225704.115125-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: salvator-common: Rename clk-multiplier to clock-controllerMarek Vasut
Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504225704.115125-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: hihope: Rename clk-multiplier to clock-controllerMarek Vasut
Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504225704.115125-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: ebisu: Rename clk-multiplier to clock-controllerMarek Vasut
Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504225704.115125-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: draak: Rename clk-multiplier to clock-controllerMarek Vasut
Use standard clock-controller node name for the CS2000-CP. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504225704.115125-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r8a779md: Add Renesas R-Car R8A779MD M3Le DTsNguyen Tran
Add support for the Renesas R-Car M3Le (R8A779MD) SoC, a variant of the R-Car M3-N (R8A77965) SoC. The Renesas M3Le SoC is a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. Signed-off-by: Nguyen Tran <nguyen.tran.pz@bp.renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504144534.43745-7-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: Simplify AA1024XD12 display DTOMarek Vasut
Move all differences into panel-aa104xd12.dtsi, rename OF_GRAPH links to generic lvds_panel_out and lvds_panel_in names, and parametrize the LVDS output in use using RENESAS_LVDS_OUTPUT macro. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260504143751.42753-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable PCIeLad Prabhakar
Enable the PCIE1 slot available on the RZ/V2N EVK. Note, the PCIE_REFCLK comes from 5L35023B versa clock generator, once the support for this clock generator is added, the fixed clock node can be removed and can be replaced with a reference to the clock generator. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260501105116.33452-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g056: Add PCIe nodeLad Prabhakar
Add PCIe node to Renesas RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260501105116.33452-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: rz-smarc-du-adv7513: Simplify DU port configurationLad Prabhakar
The SoC dtsi already defines the du node with its ports hierarchy, including the du_out_rgb endpoint node under port@0. There is no need to redefine the entire ports/port@0 structure in the board-level dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260420132211.1350656-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g087: Add MTU3 supportCosmin Tanislav
The Renesas RZ/N2H (R9A09G087) SoC has an MTU3 block. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260410163530.383818-11-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g077: Add MTU3 supportCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) SoC has an MTU3 block. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260410163530.383818-10-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a07g0{43,44,54}: Remove TCIU8 interrupt from MTU3Cosmin Tanislav
The TCIU8 interrupt used to be documented in earlier revisions of the user manuals, but has since been removed. The corresponding entry is now marked as reserved in the interrupt mapping tables of all supported SoCs. - Page 486, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2UL Rev.1.40 User Manual - Page 363, Table 8.2 Interrupt Mapping (6/13) in the Renesas RZ/Five Rev.1.30 User Manual - Page 528, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2L and RZ/G2LC Rev.1.50 User Manual - Page 540, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/V2L Rev.1.50 User Manual Remove the TCIU8 interrupt. This does not cause any breakage as the driver does not make use of the interrupts. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260410163530.383818-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodesTommaso Merciai
Add vspd{0,1} nodes to the RZ/G3E SoC DTSI. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://patch.msgid.link/46547aaff3cdb8ea6e17cf1fdec699d83a1cd71b.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-31arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodesTommaso Merciai
Add fcpvd{0,1} nodes to the RZ/G3E SoC DTSI. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://patch.msgid.link/1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-30Merge commit 'kvm-vmenter-load-store-regs' into HEADPaolo Bonzini
Convert the repeated register save/restore sequences into macros, trading some level of implementation trickiness for conciseness (more than one register can be saved/restored with one invocation) and a smaller chance of cut and paste errors between VMX and SVM files. This becomes more useful with the upcoming support for APX, which would need to add 32 lines to the VM entry/exit paths. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-30KVM: SEV: Macrofy GPR swapping in __svm_sev_es_vcpu_run()Chang S. Bae
Convert the SEV-ES entry code to use macros for saving guest GPRs, following VMX/SVM paths. Drop now-unused register offsets and __VCPU_REGS_* defines. No functional change intended. Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Link: https://patch.msgid.link/20260512011502.53072-4-chang.seok.bae@intel.com/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-30KVM: SVM: Macrofy GPR swapping in __svm_vcpu_run()Chang S. Bae
Convert the register save/restore sequences in the SVM entry into macros, following the VMX code. Drop the now-redundant register offset defines. No functional change intended. Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Link: https://patch.msgid.link/20260512011502.53072-3-chang.seok.bae@intel.com/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-19 16:09:09 +0000